Synplify to Quartus IO standard

Discussion in 'VHDL' started by Pierre-Louis, Mar 14, 2005.

  1. Pierre-Louis

    Pierre-Louis Guest

    Hi everybody,
    is there any means to pass IO standard constraints, as "LVDS", as I do for location constraints, from Symplify (Amplify) to
    Quartus??
    Thanks,
    Pierre-Louis
     
    Pierre-Louis, Mar 14, 2005
    #1
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  2. Pierre-Louis wrote:

    > is there any means to pass IO standard constraints, as "LVDS", as I do
    > for location constraints, from Symplify (Amplify) to Quartus??


    This can be done with code attributes or constraint
    files that touch the synthesis .edf netlist.

    I prefer to keep my code and .edf files independent of device
    attributes, as they are a continuous source of version mismatch errors.

    Consider letting Quartus place and route a clean
    ..edf file from Synplify.

    Once you get that to pass static timing, fix up the the pins
    and IOs in Quartus and run again.

    -- Mike Treseler
     
    Mike Treseler, Mar 14, 2005
    #2
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  3. Pierre-Louis

    Pierre-Louis Guest

    Thank you for your answer;
    my goal was to make all the constraint job under Synplify, so I can create a new and clean Quartus project each time I need,
    with the TCL file generated by Synplify making all the job. I have a lot of FPGA to synthetise, with few differences between
    them, and I don't want to work with Quartus in each directory.

    I have no problem of "portability" of my code, as the target FPGA is settled for years.
    May I pass from Synplify constraints (unknowned by Synplify, such as IO standard) in the code or in the "scope" file???
    I have partially solved the problem by creating manually a tcl file that I launch once the project is created and open in
    Quartus... That can be easily automatized.
    Pierre-Louis


    Mike Treseler wrote:

    > Pierre-Louis wrote:
    >
    >> is there any means to pass IO standard constraints, as "LVDS", as I do
    >> for location constraints, from Symplify (Amplify) to Quartus??

    >
    >
    > This can be done with code attributes or constraint
    > files that touch the synthesis .edf netlist.
    >
    > I prefer to keep my code and .edf files independent of device
    > attributes, as they are a continuous source of version mismatch errors.
    >
    > Consider letting Quartus place and route a clean
    > .edf file from Synplify.
    >
    > Once you get that to pass static timing, fix up the the pins
    > and IOs in Quartus and run again.
    >
    > -- Mike Treseler
     
    Pierre-Louis, Mar 14, 2005
    #3
  4. Pierre-Louis wrote:
    > Thank you for your answer;

    You are welcome.

    > my goal was to make all the constraint job under Synplify, so I can
    > create a new and clean Quartus project each time I need, with the TCL
    > file generated by Synplify making all the job. I have a lot of FPGA to
    > synthetise, with few differences between them, and I don't want to work
    > with Quartus in each directory.


    You can save a Quartus flow as
    a tcl script or write your own.
    If you don't use Quartus each time,
    how will you do final placement
    and static timing for each design?

    > May I pass from Synplify constraints (unknowned by Synplify, such as IO
    > standard) in the code or in the "scope" file???


    I have no pertinent experience.
    I expect that Altera and Synplify
    have documents about this interface.

    > I have partially solved the problem by creating manually a tcl file that
    > I launch once the project is created and open in Quartus... That can be
    > easily automatized.


    I agree. The whole process can be automated.
    But consider walking through it
    manually a time or two.
    Good luck.

    -- Mike Treseler
     
    Mike Treseler, Mar 14, 2005
    #4
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