Synthesis / analysis takes long time.

Discussion in 'VHDL' started by flouger@gmail.com, Oct 17, 2006.

  1. Guest

    --I dont get any errors but when I go to compile it takes forever
    -- this is the following code
    -- I was wondering what I am doing wrong.
    ---------------------------------------------------
    library ieee; -- component #1
    use ieee.std_logic_1164.all;
    USE ieee.numeric_std.all;


    entity clockdisplay is
    port( MAX_SW1: in std_logic_VECTOR (1 downto 0);
    MAX_SW2: in std_logic_vector ( 5 downto 0);
    MAX_ONES: out std_logic_vector(6 downto 0);
    MAX_TENS: out std_logic_vector(6 downto 0)
    );
    end clockdisplay;


    -----------------------------------------
    ----------------------------------------
    architecture behv of clockdisplay is
    -- Declerations of stuff to be used later
    type FORMAT is (BLANK, MINUTE, HOUR, MILITARY); --what are we working
    with yay enumerators
    ----------------------------------------
    --Validate Function
    --Takes in the limit and the std_logic vector
    --returns an integer or 70 if the logic vector is over the limit
    --------------------------------------
    function Validate ( limit : integer;
    input : in std_logic_vector ( 5 downto 0)
    ) return integer
    is
    variable ret: integer;
    begin
    ret := to_integer(unsigned(input));
    if to_integer(unsigned(input)) > limit then
    ret := 70;
    else
    end if;
    return ret;
    end Validate;
    ----------------------------------------------------------
    -- Display function takes an integer and returns an output
    -- To be used in a led on altera up2
    -- a
    -- ---
    -- f | | b
    -- --- g
    -- e | | c
    -- ---
    -- d
    -- return type is abcdefg

    function Display ( number : integer range 0 to 15)
    return std_logic_vector;
    function Display ( number : integer range 0 to 15)
    return std_logic_vector is
    variable digit: std_logic_vector(6 downto 0);
    begin --- this takes a very long time to compile not really sure why
    -- abcdefg gfedcba
    if number = 0 then digit := "0111111"; --"1111110"; -- 0 126 --
    "0111111"; --
    elsif number = 1 then digit := "0000110"; --"0110000"; -- 1 48
    "0000110"; --
    elsif number = 2 then digit := "1011011"; --"1101101"; -- 2 109
    "1011011"; --
    elsif number = 3 then digit := "1001111"; --"1111001"; -- 3 121
    "1001111"; --
    elsif number = 4 then digit := "1100110"; --"0110011"; -- 4 51
    "1100110"; --
    elsif number = 5 then digit := "1101101"; --"1011011"; -- 5 91
    "1101101"; --
    elsif number = 6 then digit := "1111101"; --"1011111"; -- 6 95
    "1111101"; --
    elsif number = 7 then digit := "0000111"; --"1110000"; -- 7 112 70
    "0000111"; --
    elsif number = 8 then digit := "1111111"; --"1111111"; -- 8 127 7F
    "1111111"; --
    elsif number = 9 then digit := "1101111"; --"1111011"; -- 9 123 7B
    "1101111"; --
    elsif number = 10 then digit := "1111001"; --"1001111"; -- E 79 4F
    "1111001"; --
    else digit := "0000000"; --"0000000"; -- Blank "0000000"; --
    end if;
    return digit;
    end Display;
    ----- end of validate function
    --- the main area of the program.
    begin
    process(MAX_SW1,MAX_SW2)
    variable DisplayType: FORMAT;
    variable Time: integer range 0 to 75;
    variable Ones: integer range 0 to 15;
    variable Tens: integer range 0 to 15;

    begin
    -- factory design pattern i think
    -- there is no need to do this other than to get familure with case
    statements
    case MAX_SW1 is
    when "00" => DisplayType := BLANK;
    when "01" => DisplayType := MINUTE;
    when "10" => DisplayType := HOUR;
    when others => DisplayType := MILITARY;
    end case;
    -- I am now friends with case statements.

    -- the if block
    if DisplayType = BLANK THEN
    time := 71; -- blank display
    ELSIF DisplayType = MINUTE then
    time := validate(59,MAX_SW2); -- 0 to 59
    ELSIF DisplayType = HOUR then
    time := validate(11,MAX_SW2)+1; --1 to 12
    ELSe --DisplayType = MILITARY then
    time := validate(23,MAX_SW2)+1; --1 to 24

    end if;
    ---


    if(time=71) then --blank the display
    ones := (11);
    tens := (11);
    elsif(time > 60) then --this should be 59 but it takes 5 min to
    compile ugh
    ones := (10);
    tens := (10);
    else
    ones := time mod 10 ;
    tens := time / 10;
    end if;

    MAX_Ones <= Display(ones);
    MAX_TENS <= Display(tens);
    end process;
    end behv;
    , Oct 17, 2006
    #1
    1. Advertising

  2. schrieb:

    > --I dont get any errors but when I go to compile it takes forever
    > -- this is the following code
    >


    > ones := time mod 10 ;
    > tens := time / 10;


    These two operators are a bit heavy for your tool. A / 2^n is very easy
    to implement (by shifting), A/10 in one clock cycle (your have no
    registers, no clock so all operations have to be done within one clock
    cycle) has to be considered evil. Same applies for the mod function.

    bye Thomas
    Thomas Stanka, Oct 17, 2006
    #2
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. Brent
    Replies:
    2
    Views:
    807
    Brent
    Oct 24, 2005
  2. Delete takes a long time

    , Dec 28, 2005, in forum: ASP .Net
    Replies:
    1
    Views:
    3,559
    Peter Rilling
    Dec 28, 2005
  3. =?Utf-8?B?cHJhc2hhbnRo?=
    Replies:
    4
    Views:
    495
    Lau Lei Cheong
    Jan 20, 2006
  4. Son KwonNam
    Replies:
    3
    Views:
    2,288
    Steve Horsley
    May 12, 2004
  5. ptouch
    Replies:
    0
    Views:
    251
    ptouch
    Jul 20, 2004
Loading...

Share This Page