synthesis report

Discussion in 'VHDL' started by ricky, Oct 21, 2004.

  1. ricky

    ricky Guest

    Hi,

    I would like to know the meaning of the synthesis tool message.



    +---------------------------------------------------------------------------
    ----+
    | design_A
    |

    |---------------------------------------------------------------------------
    ------|
    | Cell area | Total area | Late slack | Early slack

    |----------------+-----------------+----------------+-----------------------
    ----|
    | 10075.77 | 10075.77 | 5.5432 | 0.6868
    |

    +---------------------------------------------------------------------------
    -----+


    What is the difference between early slack and late slack.


    Thanks in advance.
    ricky
     
    ricky, Oct 21, 2004
    #1
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