Synthesis warning

[VHDL_lover]

Hi guys
I am sorry for long post,but I really need your help.

I Made a Microprocessor and simulation is fine.
But during Synthesis it is giving some warning about alu.

Warning: A MUX_OP was not inferred for the case
in routine alu_ent1 line 86 in file '/export/home1/test/alu2.vhd'
because the ratio of MUX_OP data inputs to unique data inputs is 5, which
exceeds the . (HDL-393)

I dont think I can ignore this warning?Please give me reason and solution
for this.here is the code for ALU.



library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

use work.alu_p.all;
use work.all;

entity alu_ent1 is
port(a_alu ,b_alu :in std_logic_vector(15 downto 0);
c_alu: out std_logic_vector(15 downto 0);
sel_alu :in std_logic_vector(4 downto 0);
reset: in std_logic;
Z: out std_logic );


end alu_ent1;



architecture alu of alu_ent1 is

signal flag :std_logic;
begin
P: process (sel_alu,reset,a_alu,b_alu)
variable tempA:std_logic_vector(16 downto 0);
variable tempB:std_logic_vector(16 downto 0);
variable temp:std_logic_vector(16 downto 0);

begin
If (reset='1')then
c_alu<="0000000000000000";
end if ;
case sel_alu is

when alu_and=>
c_alu<=a_alu and b_alu;


when alu_or=>
c_alu<= a_alu or b_alu ;


when alu_xor=>
c_alu<=a_alu xor b_alu ;


when alu_add=>

tempA := '0' & a_alu;
tempB := '0' & b_alu ;
temp := tempA + tempB ;
c_alu <= temp(15 downto 0) ;
flag <= temp(16);


when alu_sub=>
if (a_alu>=b_alu) then

c_alu<= a_alu - b_alu ;

else
c_alu<=b_alu- a_alu ;
flag<='1';
end if;
when alu_eq =>
c_alu<=a_alu;

when alu_compare_eq=>
if (a_alu = b_alu) then
Z<='1';
else
Z<='0';
end if;


when alu_compare_neq=>

if (a_alu = b_alu) then
Z<='0';
else
Z<='1';
end if;


when alu_compare_greater=>
if (a_alu > b_alu) then
Z<='1';
else
Z<='0';
end if;

when alu_compare_lesser=>

if (a_alu < b_alu) then Z<='1';
else
Z<='0';
end if;

when alu_compare_greateroreq=>

if (a_alu >= b_alu) then
Z<='1';
else
Z<='0';
end if;

when alu_compare_lesseoreq =>

if (a_alu <= b_alu) then
Z<='1';
else
Z<='0';
end if;

when alu_left_shift =>


c_alu<=b_alu(14 downto 0) & '0';

when alu_right_shift =>

c_alu<='0' & b_alu(15 downto 1);

when alu_left_rotate =>
c_alu<=b_alu(14 downto 0) & b_alu(15 );

when alu_right_rotate =>

c_alu<=b_alu(0) & b_alu(15 downto 1);

when alu_arith_right =>

c_alu(15)<=b_alu(15) ;
c_alu(14 downto 0) <= '0' & b_alu(14 downto 1);

when alu_not_C => c_alu<=not b_alu(15 downto 0);


when alu_C_PC=> c_alu<=a_alu;
when alu_PC_C=>
c_alu<=b_alu;

when alu_reset_C=>

c_alu<="0000000000000000";

when others=>null;

end case;
end process P;
end alu;

 

[mike_treseler]

If you intend a combinational process, take this out:

--If (reset='1')then
--c_alu<="0000000000000000";
--end if ;

If you intend a synchronous process, add a clock:

If (reset='1') then
c_alu<="0000000000000000";
elsif rising_edge (clk) then
case sel_alu is
-- etc etc
end if;

-- Mike Treseler

 

[wishdo]

which software do you use to synthesis?

 

[wishdo]

which software do you use to synthesis?