tcl, modelsim and vhdl generics

Discussion in 'VHDL' started by Riyaz, Apr 23, 2004.

  1. Riyaz

    Riyaz Guest

    Hi there,

    Is there a way of updating vhdl generic values in a testbench at successive
    iterations of a Tcl script? I have a testbench with the entity having a
    generic declaration. I wish to run the same testbench multiple times with a
    different value for the generic each time. I am using modelsim and
    executing a Tcl macro to run the testbench.

    Kind regards
    Riyaz, Apr 23, 2004
    #1
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  2. On Fri, 23 Apr 2004 20:26:36 +0100, "Riyaz"
    <> wrote:

    >Hi there,
    >
    >Is there a way of updating vhdl generic values in a testbench at successive
    >iterations of a Tcl script? I have a testbench with the entity having a
    >generic declaration. I wish to run the same testbench multiple times with a
    >different value for the generic each time. I am using modelsim and
    >executing a Tcl macro to run the testbench.


    Read the docs on the [vsim] command, particularly the -g and -G
    options which allow you to patch generics from the command line.

    It's also possible, and perhaps rather more fun, to parameterise
    the design using deferred constants in a package. These deferred
    constants can then be initialised from a file, or - even more fun -
    from data piped from a Tcl script to the simulator's stdin channel.
    --
    Jonathan Bromley

    Jonathan Bromley
    Jonathan Bromley, Apr 23, 2004
    #2
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