The following signals are missing in the process sensitivity list

Discussion in 'VHDL' started by antonio bergnoli, Dec 16, 2005.

  1. hi,
    using xilinx xst i noticed that the message:

    "The following signals are missing in the process sensitivity list:...."

    and following a list of signals readed inside a process; but I _don't_
    want to trigger the process with these signals, i just want to build
    synchronous machine. Of course this is not a problem but this warning is
    somewhat 'strange'. At least for me.
    antonio bergnoli, Dec 16, 2005
    #1
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  2. antonio bergnoli

    Zara Guest

    On 16 Dec 2005 11:30:16 +0100, antonio bergnoli <>
    wrote:

    >hi,
    >using xilinx xst i noticed that the message:
    >
    >"The following signals are missing in the process sensitivity list:...."
    >
    >and following a list of signals readed inside a process; but I _don't_
    >want to trigger the process with these signals, i just want to build
    >synchronous machine. Of course this is not a problem but this warning is
    >somewhat 'strange'. At least for me.



    Without context, it is difficult to answer.

    But let´s give it a try:

    if you write

    process(clock)
    begin
    if rising_edge(clock) then
    output<=input;
    end if;
    end process;

    everything is OK.

    If you write

    process(clock)
    begin
    output<=input;
    end process;

    then you will have the style of error/warning stated by the subject.

    Putting a signal in the sensitivity list is information for the
    compiler, but makes no default opeartion by itself

    Hope this helps,

    Zara
    Zara, Dec 16, 2005
    #2
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  3. > "The following signals are missing in the process sensitivity list:...."


    To design a synchronous machine, you need to clearly distinguish between
    combinational logic and registers. See
    http://mikro.e-technik.uni-ulm.de/vhdl/anl-engl.syn/html/node6.htm for
    instance.

    By default, every signal entering the combinational logic should be listed
    in the sensitivity list. That is essentially because of VHDL simulation
    semantics : the kernel reactivates the evaluation of the processes content
    each "time" ( it may be delta cycles) these signal change their value. If
    you do not respect this, you can have mismatches between simulation and
    synthesis.

    I clearly understand that this is not so natural : as you said, you do
    know that your machine will be synchronous, and having to be so precise
    for signal changes is somehow odd in this context : but it is not if you
    consider the wide spectrum of things you can do with VHDL, that may be
    asynchronous.

    For you information, there are other approaches to synchronous design,
    much more clean, such as dedicated "synchronous languages" (Esterel,
    Lustre, Signal), and in some extend "statecharts".

    Hope this helps.

    JCLL
    Jean-Christophe Le Lann, Dec 16, 2005
    #3
  4. Re: The following signals are missing in the process sensitivitylist

    antonio bergnoli wrote:

    > "The following signals are missing in the process sensitivity list:...."


    -> You modelled a latch or combinational logic. If this was your
    intention, follow this hint and complete the sensitivity list. Otherwise
    simulation and synthesis may differ.


    > but I _don't_
    > want to trigger the process with these signals, i just want to build
    > synchronous machine.


    Then you did a mistake and the process is not synchronous. Use the
    template for a flipflop:

    process(reset,clock)
    begin
    if (reset='1') then
    -- do some reset
    elsif rising_edge(clock) then
    -- do something synchronous
    end if;
    end process;


    > Of course this is not a problem but this warning is
    > somewhat 'strange'.


    No, its not strange - its important! If you want to model a flipflop,
    but get a latch, there is something seriously wrong.

    Ralf
    Ralf Hildebrandt, Dec 16, 2005
    #4
  5. Hi,
    A tip for missing a few signals in sensitivity list in a combinational
    process:
    1. If you don't do simulation, everything is OK. After compilation, the
    code can be used in FPGA or ACIS without error.

    2. If you are doing simulation, the signal doesn't change in your
    combinational process (like next state process when 2 processes are
    used for a state machine), and it will cause you a lot of time
    debugging why the equation in the process is wrong (because you miss a
    signal in the sensitivity list).

    In other words, sensitivity list is only used for simulation software,
    not for final running code.

    The sensitivity list is really an unnecessary burden for any serious
    VHDL programmers. It was created in 1980' when related software and
    technology were in an infant stage, and it will be used for next 9999
    year. Every several months this subject arises somewhere by a newbie.

    Weng
    Weng Tianxiang, Dec 18, 2005
    #5
  6. Re: The following signals are missing in the process sensitivitylist

    Jean-Christophe Le Lann wrote:

    > For you information, there are other approaches to synchronous design,
    > much more clean, such as dedicated "synchronous languages" (Esterel,
    > Lustre, Signal), and in some extend "statecharts".


    It is possible to write very clean synchronous
    VHDL code using a procedural, single-process
    design style. For examples, see:

    http://home.comcast.net/~mike_treseler/


    -- Mike Treseler
    Mike Treseler, Dec 18, 2005
    #6
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