timing simulation- output equal xx - Active HDL 7.1+ISE8.2

Discussion in 'VHDL' started by MariuszK, Sep 10, 2006.

  1. MariuszK

    MariuszK Guest

    Hello,

    I have:
    Active HDL 7.1+sp2
    -DesignFlowUpdatefor7[1].1sp2.exe
    -XilinxSchematicLibrariesISE8[1].2sp2forActive-HDL7.1(..).exe
    -XilinxVHDLLibrariesISE8[1].2SP2withIPUpdate1forActiv(..).exe

    ISE 8.2+sp2

    Why, in timing simulation output signals always equal XX?
    Synthesis and implementation without warnings (errors). Simulation
    after synthesis work correctly.

    Should I install any additional packages?
    Should be used global reset?

    Problem is global (independent of module, entity, used family-Virtex1-4
    ). Below the simplest example, where this error occur:

    library IEEE;
    use IEEE.STD_LOGIC_1164.all;
    use IEEE.STD_LOGIC_UNSIGNED.all;

    entity MyTestSimple is
    port(
    CLK : in STD_LOGIC;
    in1 : in STD_LOGIC_VECTOR(7 downto 0);
    in2 : in STD_LOGIC_VECTOR(7 downto 0);
    out1 : out STD_LOGIC_VECTOR(7 downto 0)
    );
    end MyTestSimple;

    --}} End of automatically maintained section

    architecture MyTestSimple of MyTestSimple is
    begin
    process(CLK)
    begin
    if CLK'event and CLK='1' then
    -- enter your statements here --
    out1 <= in1 + in2;
    end if;
    end process;
    end MyTestSimple;

    Best Regards
    Mariusz
     
    MariuszK, Sep 10, 2006
    #1
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  2. MariuszK

    Guest

    Re: timing simulation- output equal xx - Active HDL 7.1+ISE8.2

    MariuszK wrote:
    > Hello,
    >
    > I have:
    > Active HDL 7.1+sp2
    > -DesignFlowUpdatefor7[1].1sp2.exe
    > -XilinxSchematicLibrariesISE8[1].2sp2forActive-HDL7.1(..).exe
    > -XilinxVHDLLibrariesISE8[1].2SP2withIPUpdate1forActiv(..).exe
    >
    > ISE 8.2+sp2
    >
    > Why, in timing simulation output signals always equal XX?
    > Synthesis and implementation without warnings (errors). Simulation
    > after synthesis work correctly.
    >
    > Should I install any additional packages?
    > Should be used global reset?
    >
    > Problem is global (independent of module, entity, used family-Virtex1-4
    > ). Below the simplest example, where this error occur:
    >
    > library IEEE;
    > use IEEE.STD_LOGIC_1164.all;
    > use IEEE.STD_LOGIC_UNSIGNED.all;
    >
    > entity MyTestSimple is
    > port(
    > CLK : in STD_LOGIC;
    > in1 : in STD_LOGIC_VECTOR(7 downto 0);
    > in2 : in STD_LOGIC_VECTOR(7 downto 0);
    > out1 : out STD_LOGIC_VECTOR(7 downto 0)
    > );
    > end MyTestSimple;
    >
    > --}} End of automatically maintained section
    >
    > architecture MyTestSimple of MyTestSimple is
    > begin
    > process(CLK)
    > begin
    > if CLK'event and CLK='1' then
    > -- enter your statements here --
    > out1 <= in1 + in2;
    > end if;
    > end process;
    > end MyTestSimple;
    >
    > Best Regards
    > Mariusz


    Your problem is that you are trying to add 2 std_logic_vectors. Try
    this:

    library IEEE;
    use IEEE.STD_LOGIC_1164.all;
    use IEEE.STD_LOGIC_UNSIGNED.all;


    entity MyTestSimple is
    port(
    CLK : in STD_LOGIC;
    in1 : in STD_LOGIC_VECTOR(7 downto 0);
    in2 : in STD_LOGIC_VECTOR(7 downto 0);
    out1 : out STD_LOGIC_VECTOR(7 downto 0)
    );
    end MyTestSimple;


    --}} End of automatically maintained section


    architecture MyTestSimple of MyTestSimple is
    begin
    process(CLK)
    variable sum : unsigned;
    begin
    sum := TO_UNSIGNED( in1 ) + TO_UNSIGNED( in2 );
    if CLK'event and CLK='1' then
    -- enter your statements here --
    out1 <= std_logic_vector( sum );
    end if;
    end process;
    end MyTestSimple;
     
    , Sep 11, 2006
    #2
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  3. MariuszK

    Guest

    Re: timing simulation- output equal xx - Active HDL 7.1+ISE8.2

    MariuszK wrote:
    > Hello,
    >
    > I have:
    > Active HDL 7.1+sp2
    > -DesignFlowUpdatefor7[1].1sp2.exe
    > -XilinxSchematicLibrariesISE8[1].2sp2forActive-HDL7.1(..).exe
    > -XilinxVHDLLibrariesISE8[1].2SP2withIPUpdate1forActiv(..).exe
    >
    > ISE 8.2+sp2
    >
    > Why, in timing simulation output signals always equal XX?
    > Synthesis and implementation without warnings (errors). Simulation
    > after synthesis work correctly.
    >
    > Should I install any additional packages?
    > Should be used global reset?
    >
    > Problem is global (independent of module, entity, used family-Virtex1-4
    > ). Below the simplest example, where this error occur:
    >
    > library IEEE;
    > use IEEE.STD_LOGIC_1164.all;
    > use IEEE.STD_LOGIC_UNSIGNED.all;
    >
    > entity MyTestSimple is
    > port(
    > CLK : in STD_LOGIC;
    > in1 : in STD_LOGIC_VECTOR(7 downto 0);
    > in2 : in STD_LOGIC_VECTOR(7 downto 0);
    > out1 : out STD_LOGIC_VECTOR(7 downto 0)
    > );
    > end MyTestSimple;
    >
    > --}} End of automatically maintained section
    >
    > architecture MyTestSimple of MyTestSimple is
    > begin
    > process(CLK)
    > begin
    > if CLK'event and CLK='1' then
    > -- enter your statements here --
    > out1 <= in1 + in2;
    > end if;
    > end process;
    > end MyTestSimple;
    >
    > Best Regards
    > Mariusz


    I think I made an error in my first reply. If the addition statement
    is not inside the clocking statement then I think in1 and in2 should be
    in the sensitivity list.

    Charles
     
    , Sep 11, 2006
    #3
  4. MariuszK

    Guest

    Re: timing simulation- output equal xx - Active HDL 7.1+ISE8.2

    wrote:
    > MariuszK wrote:
    > > Hello,
    > >
    > > I have:
    > > Active HDL 7.1+sp2
    > > -DesignFlowUpdatefor7[1].1sp2.exe
    > > -XilinxSchematicLibrariesISE8[1].2sp2forActive-HDL7.1(..).exe
    > > -XilinxVHDLLibrariesISE8[1].2SP2withIPUpdate1forActiv(..).exe
    > >
    > > ISE 8.2+sp2
    > >
    > > Why, in timing simulation output signals always equal XX?
    > > Synthesis and implementation without warnings (errors). Simulation
    > > after synthesis work correctly.
    > >
    > > Should I install any additional packages?
    > > Should be used global reset?
    > >
    > > Problem is global (independent of module, entity, used family-Virtex1-4
    > > ). Below the simplest example, where this error occur:
    > >
    > > library IEEE;
    > > use IEEE.STD_LOGIC_1164.all;
    > > use IEEE.STD_LOGIC_UNSIGNED.all;
    > >
    > > entity MyTestSimple is
    > > port(
    > > CLK : in STD_LOGIC;
    > > in1 : in STD_LOGIC_VECTOR(7 downto 0);
    > > in2 : in STD_LOGIC_VECTOR(7 downto 0);
    > > out1 : out STD_LOGIC_VECTOR(7 downto 0)
    > > );
    > > end MyTestSimple;
    > >
    > > --}} End of automatically maintained section
    > >
    > > architecture MyTestSimple of MyTestSimple is
    > > begin
    > > process(CLK)
    > > begin
    > > if CLK'event and CLK='1' then
    > > -- enter your statements here --
    > > out1 <= in1 + in2;
    > > end if;
    > > end process;
    > > end MyTestSimple;
    > >
    > > Best Regards
    > > Mariusz

    >
    > Your problem is that you are trying to add 2 std_logic_vectors. Try
    > this:
    >
    > library IEEE;
    > use IEEE.STD_LOGIC_1164.all;
    > use IEEE.STD_LOGIC_UNSIGNED.all;
    >
    >
    > entity MyTestSimple is
    > port(
    > CLK : in STD_LOGIC;
    > in1 : in STD_LOGIC_VECTOR(7 downto 0);
    > in2 : in STD_LOGIC_VECTOR(7 downto 0);
    > out1 : out STD_LOGIC_VECTOR(7 downto 0)
    > );
    > end MyTestSimple;
    >
    >
    > --}} End of automatically maintained section
    >
    >
    > architecture MyTestSimple of MyTestSimple is
    > begin
    > process(CLK)
    > variable sum : unsigned;
    > begin
    > sum := TO_UNSIGNED( in1 ) + TO_UNSIGNED( in2 );
    > if CLK'event and CLK='1' then
    > -- enter your statements here --
    > out1 <= std_logic_vector( sum );
    > end if;
    > end process;
    > end MyTestSimple;


    I am not doing too well as an advisor today. Another error in my reply
    is that I didn't dimension the unsigned variable sum. It should have
    the same range as out1.
     
    , Sep 11, 2006
    #4
  5. MariuszK

    Guest

    Re: timing simulation- output equal xx - Active HDL 7.1+ISE8.2

    wrote:
    > MariuszK wrote:
    > > Hello,
    > >
    > > I have:
    > > Active HDL 7.1+sp2
    > > -DesignFlowUpdatefor7[1].1sp2.exe
    > > -XilinxSchematicLibrariesISE8[1].2sp2forActive-HDL7.1(..).exe
    > > -XilinxVHDLLibrariesISE8[1].2SP2withIPUpdate1forActiv(..).exe
    > >
    > > ISE 8.2+sp2
    > >
    > > Why, in timing simulation output signals always equal XX?
    > > Synthesis and implementation without warnings (errors). Simulation
    > > after synthesis work correctly.
    > >
    > > Should I install any additional packages?
    > > Should be used global reset?
    > >
    > > Problem is global (independent of module, entity, used family-Virtex1-4
    > > ). Below the simplest example, where this error occur:
    > >
    > > library IEEE;
    > > use IEEE.STD_LOGIC_1164.all;
    > > use IEEE.STD_LOGIC_UNSIGNED.all;
    > >
    > > entity MyTestSimple is
    > > port(
    > > CLK : in STD_LOGIC;
    > > in1 : in STD_LOGIC_VECTOR(7 downto 0);
    > > in2 : in STD_LOGIC_VECTOR(7 downto 0);
    > > out1 : out STD_LOGIC_VECTOR(7 downto 0)
    > > );
    > > end MyTestSimple;
    > >
    > > --}} End of automatically maintained section
    > >
    > > architecture MyTestSimple of MyTestSimple is
    > > begin
    > > process(CLK)
    > > begin
    > > if CLK'event and CLK='1' then
    > > -- enter your statements here --
    > > out1 <= in1 + in2;
    > > end if;
    > > end process;
    > > end MyTestSimple;
    > >
    > > Best Regards
    > > Mariusz

    >
    > Your problem is that you are trying to add 2 std_logic_vectors. Try
    > this:
    >
    > library IEEE;
    > use IEEE.STD_LOGIC_1164.all;
    > use IEEE.STD_LOGIC_UNSIGNED.all;
    >
    >
    > entity MyTestSimple is
    > port(
    > CLK : in STD_LOGIC;
    > in1 : in STD_LOGIC_VECTOR(7 downto 0);
    > in2 : in STD_LOGIC_VECTOR(7 downto 0);
    > out1 : out STD_LOGIC_VECTOR(7 downto 0)
    > );
    > end MyTestSimple;
    >
    >
    > --}} End of automatically maintained section
    >
    >
    > architecture MyTestSimple of MyTestSimple is
    > begin
    > process(CLK)
    > variable sum : unsigned;
    > begin
    > sum := TO_UNSIGNED( in1 ) + TO_UNSIGNED( in2 );
    > if CLK'event and CLK='1' then
    > -- enter your statements here --
    > out1 <= std_logic_vector( sum );
    > end if;
    > end process;
    > end MyTestSimple;


    I am not doing too well as an advisor today. Another error in my reply
    is that I didn't dimension the unsigned variable sum. It should have
    the same range as out1.
     
    , Sep 11, 2006
    #5
  6. MariuszK

    MariuszK Guest

    Re: timing simulation- output equal xx - Active HDL 7.1+ISE8.2


    > I think I made an error in my first reply. If the addition statement
    > is not inside the clocking statement then I think in1 and in2 should be
    > in the sensitivity list.
    >
    > Charles


    I added in1 and in2 to sensitivity list of process. Result:eek:utput
    signal still equal XX. Any other ideas?
     
    MariuszK, Sep 11, 2006
    #6
  7. MariuszK

    KJ Guest

    Re: timing simulation- output equal xx - Active HDL 7.1+ISE8.2

    MariuszK wrote:
    > Problem is global (independent of module, entity, used family-Virtex1-4
    > ). Below the simplest example, where this error occur:
    >
    > library IEEE;
    > use IEEE.STD_LOGIC_1164.all;
    > use IEEE.STD_LOGIC_UNSIGNED.all;
    >
    > entity MyTestSimple is
    > port(
    > CLK : in STD_LOGIC;
    > in1 : in STD_LOGIC_VECTOR(7 downto 0);
    > in2 : in STD_LOGIC_VECTOR(7 downto 0);
    > out1 : out STD_LOGIC_VECTOR(7 downto 0)
    > );
    > end MyTestSimple;
    >
    > --}} End of automatically maintained section
    >
    > architecture MyTestSimple of MyTestSimple is
    > begin
    > process(CLK)
    > begin
    > if CLK'event and CLK='1' then
    > -- enter your statements here --
    > out1 <= in1 + in2;
    > end if;
    > end process;
    > end MyTestSimple;
    >
    > Best Regards
    > Mariusz


    As an aside, you should use ieee.numeric_std package when you do any
    sort of math it is a standard whereas "IEEE.STD_LOGIC_UNSIGNED" is not.

    But that's not the problem, and looking at your code one can not
    determine the problem so here are some areas to look at. First, in
    your simulator, navigate down to the 'MyTestSimple' entity and add CLK,
    in1, in2 and out1 to your wave window.
    - Is Clk running?
    - Are in1 and in2 what you expect them to be?
    - Are you waiting long enough after the rising edge of Clk for 'out1'
    to be valid? This number comes out of the timing report from your
    build. If it says 5ns, then don't complain that 'out' is wrong 1ps
    after the rising edge.

    If both of the above look OK but out1 is 'XX' then the problem is that
    there is something else driving 'out1'. This would have to be in some
    code other that which you posted. To find it, you need to use the
    simulator to see what other sources are driving this signal. Maybe
    something in your testbench?

    You might also want to consider changing to 'std_ulogic_vector' instead
    of 'std_logic_vector'. The difference between std_ulogic and std_logic
    is that it is not legal to have two drivers on any signal declared to
    be type 'std_ulogic' (but this is permissable with std_logic). If you
    do try to drive a std_ulogic in two places you'll either get a compiler
    error straight off or when you go to start the simulation you'll get
    the complaint and it will generally point to the offending
    parties...one of which must be wrong.

    Good luck.

    KJ
     
    KJ, Sep 11, 2006
    #7
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