to_integer can not have such operands in this contex

Discussion in 'VHDL' started by A. Kong, Oct 10, 2004.

  1. A. Kong

    A. Kong Guest

    Hi,all,

    Here is the part of code which defines the arhitecture of a fetch unit:
    =====================================================================
    architecture behavioral of fetch is
    type type_instruction_array is array(0 to 31) of std_logic_vector(31
    downto 0);

    begin
    process
    -- local variable used as a PC internally
    variable PC : std_logic_vector(31 downto 0);
    variable iaddr : integer := 0;
    variable imem : type_instruction_array;
    begin
    ....

    ====================================================================

    In the process i want to convert the PC to an integer

    I have tried the following statements:

    iaddr := to_integer(PC);
    iaddr := to_integer( To_bitvector(PC));
    iaddr := to_integer(unsigned(PC));

    I got this error messages:

    to_integer can
    not have such operands in this context.

    Well, I am not sure what is wrong here. I was following 4.2.25 of VHDL
    Faq1. Is my understanding wrong?

    Cheers,
    AK
    A. Kong, Oct 10, 2004
    #1
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  2. "A. Kong" <ahwkong2x1000-at-anti-spam-yahoo.com> wrote:
    > variable PC : std_logic_vector(31 downto 0);
    > variable iaddr : integer := 0;


    If I'm not mistaken, integer in VHDL is defined as a 32 bit signed number.
    You cannot take a 32 bit vector, convert it to unsigned, and then place it
    within an integer. It won't fit within the range. to_integer uses either
    signed or unsigned vectors, so I'd expect the first two examples you gave
    to give a different error message, though that will probably depend on your
    compiler.

    Regards,

    Pieter Hulshoff
    Pieter Hulshoff, Oct 10, 2004
    #2
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  3. A. Kong

    Moti Cohen Guest

    "A. Kong" <ahwkong2x1000-at-anti-spam-yahoo.com> wrote in message news:<41686eeb$>...
    > Hi,all,
    >
    > Here is the part of code which defines the arhitecture of a fetch unit:
    > =====================================================================
    > architecture behavioral of fetch is
    > type type_instruction_array is array(0 to 31) of std_logic_vector(31
    > downto 0);
    >
    > begin
    > process
    > -- local variable used as a PC internally
    > variable PC : std_logic_vector(31 downto 0);
    > variable iaddr : integer := 0;
    > variable imem : type_instruction_array;
    > begin
    > ...
    >
    > ====================================================================
    >
    > In the process i want to convert the PC to an integer
    >
    > I have tried the following statements:
    >
    > iaddr := to_integer(PC);
    > iaddr := to_integer( To_bitvector(PC));
    > iaddr := to_integer(unsigned(PC));
    >
    > I got this error messages:
    >
    > to_integer can
    > not have such operands in this context.
    >
    > Well, I am not sure what is wrong here. I was following 4.2.25 of VHDL
    > Faq1. Is my understanding wrong?


    I'm not sure that the "to_integer" function can be used in order to
    convert std_logic_vector to integer. If I remember correctly it can
    only be used for signed/unsigned data input.
    I usually uses the "conv_integer" conversion from the
    STD_LOGIC_UNSIGNED pacakge for peforming such operations
    (std_logic_vector -> integer). but if it is a problem you can first
    convert the std to unsigned and then to integer.

    p.s. - also check that u declared the required ieee pacakge.

    I hope that it is helpful...
    Moti.

    >
    > Cheers,
    > AK
    Moti Cohen, Oct 10, 2004
    #3
  4. A. Kong

    Alan Fitch Guest

    <snip>
    > -- local variable used as a PC internally
    > variable PC : std_logic_vector(31 downto 0);
    > variable iaddr : integer := 0;

    <snip>

    > In the process i want to convert the PC to an integer
    >
    > I have tried the following statements:
    >
    > iaddr := to_integer(PC);
    > iaddr := to_integer( To_bitvector(PC));
    > iaddr := to_integer(unsigned(PC));
    >



    The last one
    to_integer(unsigned(PC))

    looks OK. Have you said

    library IEEE;
    use IEEE.Numeric_Std.all;

    in front of your entity or architecture?

    regards

    Alan


    --
    Alan Fitch
    Consultant

    DOULOS - Developing Design Know-how
    VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project
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    Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24
    1AW, UK
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    The contents of this message may contain personal views which are not
    the
    views of Doulos Ltd., unless specifically stated.
    Alan Fitch, Oct 11, 2004
    #4
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