translate_off/on tool interoperability

[Rob Dekker]

Hi guys,

The translate_off/on pragmas are not standardized (apart from 1076.6 RTL_SYNTHESIS pragmas), but still very widely used across the
industry, to separate code for simulation from code for (RTL) synthesis.
I'm looking into tool interoperability of this pragma, and ran into the following interesting example :


entity test is
(i, clock : in bit ; o : out bit) ;
end entity test ;

architecture dff of test is
wait until ( clock = '1' and clock'event ) ;
o <= i -- synopsys synthesis_off
after 1 ns ;
-- synopsys synthesis_on
end process ;
end architecture dff ;


Note that the semicolon that closes the assignment statement is within the synthesis_off/synthesis_on pragmas.
That results in illegal VHDL (statement not terminated with a semicolon) when we ignore the code between the off/on pragmas.
I understand that 1076.6 also deems this illegal, but it specifies only the RTL_SYNTHESIS pragma, not the much more often
translate_off/on pragma's started by individual companies like Synopsys.

Tools based on Verific VHDL front-end (some 50 EDA tools) currently error out when running this example in synthesis mode (granting
the translate_off/on pragma's).
But I am not so sure about many other tools (including Synopsys DC itself).

So I have a request : Can you please try this example on your favorite synthesis and/or formal verification tool (or other tool that
is sensitive to translate_off/on pragmas) ?
I'd like to get to a point where all tools handle translate_off/on pragma's the same way.

Thanks !

Rob Dekker

 

[Dwayne Dilbeck]

Your code has anumber of syntax errors besides the issue you want to test.
Try the following insetad.

entity test is
port (i, clock : in bit ;
o : out bit) ;
end entity test ;

architecture dff of test is
begin
clkedrocess
begin
wait until ( clock = '1' and clock'event ) ;
o <= i -- synopsys translate_off
after 1 ns;
-- synopsys translate_on
end process clked;
end architecture dff ;

-------------------------------------
--IUS 6.2.s003 -- Syntax passes
--Conformal 7.2 -- Syntax error
--Cadence Incisive XE 5.2 -- Syntax error (Emulation synthesis engine)
----------------------------------------

-----------------------------
--Use the following code to pass syntax checks on all programs
------------------------------
entity test is
port (i, clock : in bit ;
o : out bit) ;
end entity test ;

architecture dff of test is
begin
clkedrocess
begin
wait until ( clock = '1' and clock'event ) ;
o <= i -- synopsys translate_off
after 1 ns
-- synopsys translate_on
;
end process clked;
end architecture dff ;

 

[Mike Treseler]

Tools based on Verific VHDL front-end (some 50 EDA tools) currently
error out when running this example in synthesis mode

My test below confirms this.

-- Mike Treseler
__________________________________
library ieee;
use ieee.std_logic_1164.all;
entity synopsys_test is
port(i, clock : in std_ulogic; o : out std_ulogic);
end entity synopsys_test;

architecture dff of synopsys_test is
begin
process (clock) is
begin
if rising_edge(clock) then
o <= i
-- synopsys synthesis_off
after 1 ns;
-- synopsys synthesis_on
end if; -- line 16
-- Quartus Error (10500): VHDL syntax error at
-- synopsys_test.vhd(16) near text "end"; expecting ";
end process;
end architecture dff;

-- Adding a space like this
-- s ynopsys synthesis_off
-- eliminates the error and quartus makes a flop just fine.

-- Mike Treseler

 

[Rob Dekker]

Thanks Mike, and Dwayne for trying the Altera and Cadence tools respectively. At least there is consistency so far (syntax error).
Can anyone run Design Compiler on this example ?
Or any other synthesis tool (XST, Synplify, Precision etc ) ?

Thanks !

Rob

 

[Rob Dekker]

Can anyone run Design Compiler on this example ?
Or any other synthesis tool (XST, Synplify, Precision etc ) ?

Here is the corrected design again (Thanks Dwayne for correcting the posted example) :

entity test is
port (i, clock : in bit ; o : out bit) ;
end entity test ;

architecture dff of test is
begin
clkedrocess
begin
wait until ( clock = '1' and clock'event ) ;
o <= i -- synopsys translate_off
after 1 ns;
-- synopsys translate_on
end process clked;
end architecture dff ;

 

[Mike Treseler]

Can anyone run Design Compiler on this example ?

If such a benevolent, vhdl-using, dc owner exists,
please run basic synthesis on this example also:

http://home.comcast.net/~mike_treseler/uart.vhd

I only need the warnings and errors.
I have had conflicting reports that dc
can/can't handle vhdl procedures.

-- Mike Treseler