translating verilog primitive to vhdl

Discussion in 'VHDL' started by EnezVeur, Mar 17, 2010.

  1. EnezVeur

    EnezVeur Guest

    Hello,
    I am quite new to verilog. I need to translate a verilog primitive to vhdl
    entity/architecture. This primitive is modelizing a latch with in, set,
    clear, hold and notifier (?) inputs. Need some help. Some examples are
    welcome
    EnezVeur, Mar 17, 2010
    #1
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  2. EnezVeur

    M. Norton Guest

    On Mar 17, 4:17 pm, "EnezVeur" <> wrote:
    > Hello,
    > I am quite new to verilog. I need to translate a verilog primitive to vhdl
    > entity/architecture. This primitive is modelizing a latch with in, set,
    > clear, hold and notifier (?) inputs. Need some help. Some examples are
    > welcome.


    It would help to be able to see the declaration you're using for the
    Verilog variant of the primitive structure. Given that, it shouldn't
    be too difficult to create a VHDL version of that.

    Best regards,
    Mark Norton
    M. Norton, Mar 17, 2010
    #2
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  3. On Wed, 17 Mar 2010 22:17:07 +0100, "EnezVeur" wrote:

    >Hello,
    >I am quite new to verilog. I need to translate a verilog primitive to vhdl
    >entity/architecture. This primitive is modelizing a latch with in, set,
    >clear, hold and notifier (?) inputs. Need some help. Some examples are
    >welcome


    Sounds very homework-ish. A notifier is an output from a Verilog
    timing check, used to signal that a timing violation has occurred.
    Sometimes a latch or flip-flop may have a notifier *input* so that
    when the notifier toggles, the storage element is loaded with X.

    Since VHDL has nothing like Verilog's UDPs, the only hope is to
    get a clear description of the Verilog primitive's functionality
    and then to write a model of that functionality from scratch
    in VHDL. Good luck.
    --
    Jonathan Bromley
    Jonathan Bromley, Mar 17, 2010
    #3
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