USB vhdl code (followup)

[Rob Maris]

Since no followups of elder messages seems to be possible, I started
this as new message.

Opencores.org provides a USB 1.1 IP in verilog. Not in VHDL.

A student of my university has created a USB 1.1 IP in VHDL.

Rob

 

[Martin Maurer]

A student of my university has created a USB 1.1 IP in VHDL.

Possible to get this code ?

Regards,

Martin

 

[Don Golding]

I would like to see the code too...

Thanks,
Don

Possible to get this code ?

Regards,

Martin

 

[Alex Gibson]

Since no followups of elder messages seems to be possible, I started
this as new message.

Opencores.org provides a USB 1.1 IP in verilog. Not in VHDL.

A student of my university has created a USB 1.1 IP in VHDL.

Rob

Are you guys going to add it to opencores.org ?