USB vhdl code (followup)

Discussion in 'VHDL' started by Rob Maris, Aug 6, 2004.

  1. Rob Maris

    Rob Maris Guest

    Since no followups of elder messages seems to be possible, I started
    this as new message.

    Opencores.org provides a USB 1.1 IP in verilog. Not in VHDL.

    A student of my university has created a USB 1.1 IP in VHDL.

    Rob
    Rob Maris, Aug 6, 2004
    #1
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  2. > A student of my university has created a USB 1.1 IP in VHDL.

    Possible to get this code ?

    Regards,

    Martin
    Martin Maurer, Aug 6, 2004
    #2
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  3. Rob Maris

    Don Golding Guest

    I would like to see the code too...

    Thanks,
    Don

    "Martin Maurer" <> wrote in message
    news:cf0e8t$3jj$04$-online.com...
    > > A student of my university has created a USB 1.1 IP in VHDL.

    >
    > Possible to get this code ?
    >
    > Regards,
    >
    > Martin
    >
    >
    Don Golding, Aug 7, 2004
    #3
  4. Rob Maris

    Alex Gibson Guest

    "Rob Maris" <> wrote in message
    news:...
    > Since no followups of elder messages seems to be possible, I started
    > this as new message.
    >
    > Opencores.org provides a USB 1.1 IP in verilog. Not in VHDL.
    >
    > A student of my university has created a USB 1.1 IP in VHDL.
    >
    > Rob


    Are you guys going to add it to opencores.org ?
    Alex Gibson, Aug 8, 2004
    #4
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