use alias in port declaration?

Discussion in 'VHDL' started by Mike Dearman, Feb 26, 2009.

  1. Mike Dearman

    Mike Dearman Guest

    I have the following vector in my design:

    signal CONTROL_PINS : std_logic_vector(69 downto 0);

    I want to connect certain bits of this vector to pins, and i want to
    give them meaningfull names, for example i want a pin called "ABC"
    connected to CONTROL_PINS(4)

    the most obvious thing i can think of is to use an alias:

    alias "ABC" is CONTROL_PINS(4);

    but i can't use "ABC" in the port declaration as it then complains
    about being declared twice.

    Am i going about this the wrong way? Suggestions welcomed

    Mike
    Mike Dearman, Feb 26, 2009
    #1
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  2. Mike Dearman

    JohnDuq

    Joined:
    Dec 9, 2008
    Messages:
    88
    Isn't the port already declared as CONTROL_PINS(4)? Thus the double declaration error.

    Are you trying to access the port from the top level as ABC? It seems if you are accessing it that way then you wouldn't have the alias, but would have ABC connected to the component instantiation. Maybe a sample of your port declaration would help; the two declarations you have shown here look correct.

    This may be useful:

    www dot vdlande.com/VHDL/aliasdec.html
    JohnDuq, Feb 26, 2009
    #2
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  3. Mike Dearman

    KJ Guest

    On Feb 26, 12:46 pm, Mike Dearman <> wrote:
    > I have the following vector in my design:
    >
    > signal  CONTROL_PINS                    : std_logic_vector(69 downto 0);
    >
    > I want to connect certain bits of this vector to pins, and i want to
    > give them meaningfull names, for example i want a pin called "ABC"
    > connected to CONTROL_PINS(4)
    >
    > the most obvious thing i can think of is to use an alias:
    >
    > alias "ABC" is CONTROL_PINS(4);
    >


    Is there some reason why simply adding the following assignment in the
    architecture is not acceptable?

    ABC <= CONTROL_PINS(4);

    It delays ABC by one simulation delta which can bite you if ABC is
    then used as some form of clock downstream and the thing being sample
    is not similarly delta delayed, but other than that...

    KJ
    KJ, Feb 26, 2009
    #3
  4. Mike Dearman

    Mike Dearman Guest

    On 26 Feb, 21:03, KJ <> wrote:
    > On Feb 26, 12:46 pm, Mike Dearman <> wrote:
    >
    > > I have the following vector in my design:

    >
    > > signal  CONTROL_PINS                    : std_logic_vector(69 downto 0);

    >
    > > I want to connect certain bits of this vector to pins, and i want to
    > > give them meaningfull names, for example i want a pin called "ABC"
    > > connected to CONTROL_PINS(4)

    >
    > > the most obvious thing i can think of is to use an alias:

    >
    > > alias "ABC" is CONTROL_PINS(4);

    >
    > Is there some reason why simply adding the following assignment in the
    > architecture is not acceptable?
    >
    > ABC <= CONTROL_PINS(4);
    >
    > It delays ABC by one simulation delta which can bite you if ABC is
    > then used as some form of clock downstream and the thing being sample
    > is not similarly delta delayed, but other than that...
    >
    > KJ


    They're bi-directional signals and i understood <= is a directional
    assignment?

    sorry, i should have mentioned the bi-directional thing in the
    original post.

    Mike
    Mike Dearman, Feb 27, 2009
    #4
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