Using a vector as an index

[M. Hamed]

Why is the Xilinx tool complaining about this (VHDL):

timer_done <= timer(data_len);

Where data_len is a 4 bit std_logic_vector, and timer is a 16 bit
std_logic_vector.

I want the tool to automatically infer a MUX with data_len as the
selector and timer as the input.

I can use a CASE statement but that is a lot of coding. I think
Verilog can happily accept that.

Thanks.

 

[Dave]

Why is the Xilinx tool complaining about this (VHDL):

timer_done <= timer(data_len);

Where data_len is a 4 bit std_logic_vector, and timer is a 16 bit
std_logic_vector.

I want the tool to automatically infer a MUX with data_len as the
selector and timer as the input.

I can use a CASE statement but that is a lot of coding. I think
Verilog can happily accept that.

Thanks.

Try this:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

-- snip

timer_done <= timer(to_integer(unsigned(data_len));

Dave