using entity attributes for pin number assignments

[Neil Zanella]

Hello,

I would like to know whether using attributes inside entity declarations
to assign pin numbers to signals as opposed to using a user constraints
file (.ucf file) is portable or whether it's a vendor specific extension.
Does the VHDL standard itself support such constructs, or are
implementations free to use attributes in implementation
define manners?

Thanks,

Neil

 

[Allan Herriman]

Hello,

I would like to know whether using attributes inside entity declarations
to assign pin numbers to signals as opposed to using a user constraints
file (.ucf file) is portable or whether it's a vendor specific extension.
Does the VHDL standard itself support such constructs, or are
implementations free to use attributes in implementation
define manners?

The VHDL standard only defines the syntax for attributes. The meaning
is up to the tool. I guess an ideal synth tool would pass any
attributes it didn't recognise straight through to the EDIF. Most
tools I've used seem to do this quite well, except XST (which knows
which attributes are supported by the back end tools).

I have successfully used attributes in an architecture to assign pin
numbers.
I have also used UCF to assign pin numbers.

I prefer the UCF, as the PCB package we use here spits out the correct
UCF (via a Perl script). I can allow the PCB designer to swap pins
(allowing for various banking and SSO rules, etc.) and I don't have to
worry about changing my VHDL source.

Regards,
Allan.

 

[Neil Zanella]

I agree with you. It seems that using the UCF file for pin assignments
is both more flexible and more portable. A design should be as independent
of the hardware it is implemented on as possible and should have the potential
to be synthesized by a variety of tools and to a variety of distinct hardware.

Regards,

Neil