VHDL Auto-stitching tool (ala emacs verilog-mode AUTOINST)

Discussion in 'VHDL' started by Mark, Jun 16, 2009.

  1. Mark

    Mark Guest

    I'm coding for the first time in 10 years in VHDL and am trying to
    find equivalents to my old verilog tool-box. One tool I found
    extremely useful was the AUTOINST features of the verilog-mode in
    emacs where it would automatically connect instance ports and where
    you could define per-instance naming rules via AUTO_TEMPLATE. I've
    discovered the port copy/port-paste as... feature in the emacs vhdl-
    mode, but am wondering if that's as close as I can get to the auto-
    instantiate feature of the verilog-mode?

    Thanks,

    Mark
    Mark, Jun 16, 2009
    #1
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  2. Mark wrote:
    > I'm coding for the first time in 10 years in VHDL and am trying to
    > find equivalents to my old verilog tool-box. One tool I found
    > extremely useful was the AUTOINST features of the verilog-mode in
    > emacs where it would automatically connect instance ports and where
    > you could define per-instance naming rules via AUTO_TEMPLATE. I've
    > discovered the port copy/port-paste as... feature in the emacs vhdl-
    > mode, but am wondering if that's as close as I can get to the auto-
    > instantiate feature of the verilog-mode?


    That's it for vhdl-mode,
    unless you can tolerate functions and variables instead.

    VHDL,Port,Copy
    VHDL,Port,Paste as instance.

    -- Mike Treseler
    Mike Treseler, Jun 16, 2009
    #2
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  3. Mark

    Jan Decaluwe Guest

    Mark wrote:
    > I'm coding for the first time in 10 years in VHDL and am trying to
    > find equivalents to my old verilog tool-box. One tool I found
    > extremely useful was the AUTOINST features of the verilog-mode in
    > emacs where it would automatically connect instance ports and where
    > you could define per-instance naming rules via AUTO_TEMPLATE. I've
    > discovered the port copy/port-paste as... feature in the emacs vhdl-
    > mode, but am wondering if that's as close as I can get to the auto-
    > instantiate feature of the verilog-mode?


    You may want to take a look at Sigasi HDT, a next generation
    (Eclipse-based) VHDL IDE. It makes instantiations much easier through
    intelligent autocompletes and by automatically generating missing signal
    declarations. It also has refactorings to add new connections
    quickly.

    http://www.sigasi.com

    --
    Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
    VHDL development, the modern way: http://www.sigasi.com
    Jan Decaluwe, Jun 16, 2009
    #3
  4. Mark

    Mark Guest

    On Jun 16, 2:09 pm, Mike Treseler <> wrote:
    > Mark wrote:
    > > I'm coding for the first time in 10 years in VHDL and am trying to
    > > find equivalents to my oldverilogtool-box.  One tool I found
    > > extremely useful was theAUTOINSTfeatures of theverilog-mode in
    > > emacs where it would automatically connect instance ports and where
    > > you could define per-instance naming rules via AUTO_TEMPLATE.   I've
    > > discovered the port copy/port-paste as... feature in the emacs vhdl-
    > > mode, but am wondering if that's as close as I can get to the auto-
    > > instantiate feature of theverilog-mode?

    >
    > That's it for vhdl-mode,
    > unless you can tolerate functions and variables instead.
    >
    > VHDL,Port,Copy
    > VHDL,Port,Paste as instance.
    >
    >       -- Mike Treseler


    Thought I'd follow-up for the next person looking for autostitch in
    vhdl-mode. Just discovered vhdl-compose-wire-components in the emacs
    mode which goes a bit further than just port-copy-and-paste. Not sure
    all its capabilities yet, but it filled out all my signals, which was
    very nice.

    Mark
    Mark, Jul 7, 2009
    #4
  5. Mark wrote:

    > Thought I'd follow-up for the next person looking for autostitch in
    > vhdl-mode. Just discovered vhdl-compose-wire-components in the emacs
    > mode which goes a bit further than just port-copy-and-paste. Not sure
    > all its capabilities yet, but it filled out all my signals, which was
    > very nice.


    Yes. VHDL-compose- fills in signals and wires up identical names.
    Can set for direct or indirect instances.
    Handy for structural code, but I'm a procedural guy.

    -- Mike Treseler
    Mike Treseler, Jul 15, 2009
    #5
  6. Mark

    omara007

    Joined:
    Jun 30, 2008
    Messages:
    10

    But how do you use this (vhdl-compose-wire-components) exactly ? .. can you give an example ? ..
    By the way, is (emacs-mode) the same as the (fundamental-mode) ?
    omara007, Jan 6, 2010
    #6
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