Modelsim problem - mixed VHDL,Verilog & VHO

Discussion in 'VHDL' started by Mark McDougall, Nov 7, 2006.

  1. I'm having problems getting a simulation running. Here's the recipe...

    Quartus output VHO file - contains VHDL & Verilog components.
    Testbench components - VHDL & Verilog components.

    Note (and I *think* this is part of the problem) the VHO file contains a
    certain verilog modle, whilst the testbench also contains an instance of
    the same module, albeit with *different* parameter values.

    Attempting to start the simulation under ModelSim ('vsim') loads a bunch
    of structures from the library, and then halts with an error that just
    does *not* make any sense at all!

    The error is "irda_peripheral.v(155) The width (1) of VHDL port
    'addr_cnt_out_2' does not match the width (5) of its Verilog connection
    (3rd connection)".

    This error occurs in the file that contains a 2nd instance of the
    verilog module, and the 3rd connection is indeed a vector whose width is
    specified with a parameter - which incidently differs from the value for
    the instance inside the VHO file.

    However:

    * addr_cnt_out is internal to the VHO and not connected to the instance
    in this file at all.
    * neither of the parameters specify a width of '1' for the vector.

    I suspect Modelsim is getting confused between the instance in the VHO
    file and the instance in irda_peripheral.v and is having trouble wiring
    up the ports?!?

    Anyone else had a similar experience?

    Regards,

    --
    Mark McDougall, Engineer
    Virtual Logic Pty Ltd, <http://www.vl.com.au>
    21-25 King St, Rockdale, 2216
    Ph: +612-9599-3255 Fax: +612-9599-3266
     
    Mark McDougall, Nov 7, 2006
    #1
    1. Advertising

  2. Mark McDougall wrote:
    > I'm having problems getting a simulation running. Here's the recipe...
    > Quartus output VHO file - contains VHDL & Verilog components.
    > Testbench components - VHDL & Verilog components.


    Maybe you need a mixed language license from Mentor.

    -- Mike Treseler
     
    Mike Treseler, Nov 7, 2006
    #2
    1. Advertising

  3. Mike Treseler wrote:

    > Maybe you need a mixed language license from Mentor.


    Already have, been running behavioural simulation with mixed-language
    for yonks!

    Regards,

    --
    Mark McDougall, Engineer
    Virtual Logic Pty Ltd, <http://www.vl.com.au>
    21-25 King St, Rockdale, 2216
    Ph: +612-9599-3255 Fax: +612-9599-3266
     
    Mark McDougall, Nov 7, 2006
    #3
  4. I should probably also add, I have done successful post-PAR simulation
    using VHO in the past on an ancestor of this very design! I didn't have
    the verilog module that is seemingly causing my current problems...

    Regards,

    --
    Mark McDougall, Engineer
    Virtual Logic Pty Ltd, <http://www.vl.com.au>
    21-25 King St, Rockdale, 2216
    Ph: +612-9599-3255 Fax: +612-9599-3266
     
    Mark McDougall, Nov 7, 2006
    #4
  5. Mark McDougall wrote:

    > I'm having problems getting a simulation running. Here's the
    > recipe...
    >
    > Quartus output VHO file - contains VHDL & Verilog components.
    > Testbench components - VHDL & Verilog components.
    >
    > Note (and I *think* this is part of the problem) the VHO file
    > contains a certain verilog modle, whilst the testbench also contains
    > an instance of the same module, albeit with *different* parameter
    > values.


    Have a look in the ModelSim User's Manual, in chapter 'Compiling
    Verilog Files'. There is a paragraph "Handling sub-modules with
    common names". It mentions the special meaning of the vsim option
    -L work:

    "When you specify -L work first in the search library arguments you
    are directing vsim to search for the instantiated module or UDP in
    the library that contains the module that does the instantiation."

    I'm not sure if this is exactly your problem.

    --
    Paul.
    www.aimcom.nl
    email address: switch x and s
     
    Paul Uiterlinden, Nov 8, 2006
    #5
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. Akshaye
    Replies:
    1
    Views:
    775
    Hemant Gupta
    Feb 9, 2004
  2. botao

    mixed Verilog/VHDL design

    botao, Jul 7, 2004, in forum: VHDL
    Replies:
    6
    Views:
    7,364
    Eric Smith
    Jul 8, 2004
  3. nemgreen

    Re: mixed Verilog/VHDL design

    nemgreen, Jul 8, 2004, in forum: VHDL
    Replies:
    3
    Views:
    3,500
    Rob Dekker
    May 3, 2005
  4. Just an Illusion

    Re: mixed Verilog/VHDL design

    Just an Illusion, Jul 8, 2004, in forum: VHDL
    Replies:
    0
    Views:
    691
    Just an Illusion
    Jul 8, 2004
  5. Steven Derrien
    Replies:
    2
    Views:
    3,876
    Steven Derrien
    Jul 13, 2006
Loading...

Share This Page