VHDL bidirectional buffer?

Discussion in 'VHDL' started by John5788, Jun 17, 2008.

  1. John5788

    John5788

    Joined:
    Jun 17, 2008
    Messages:
    1
    I am trying to design the Lattice CPLD: LC4032v to kind of act as a buffer for now, and am having problems dealing with the bidirectional ports.

    I programmed the ports to direct data one way or another based on a clock. Here is a sample of what I am doing:

    Code (Text):

    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_arith.all;
    use ieee.std_logic_unsigned.all;

    entity OneToOne is
        port (
                   
            -- Inputs
            A0, A1: in std_logic;

            -- Clocks
            CLK0: in std_logic;

            -- Outputs
            B0, B1: out std_logic;

            -- Bidirectional ports
            A8, A9, B8, B9: inout std_logic);
           

    end OneToOne;

    architecture behavioral of OneToOne is
    begin

        B0 <= A0;
        B1 <= A1;
       
        process(CLK0)
        begin
           
            if(CLK0 = '0' AND CLK0'event) then
                B8 <= A8;
                B9 <= A9;

            elsif(CLK0 = '1' AND CLK0'event) then
                A8 <= B8;
                A9 <= B9;

            end if;
       
        end process;
       
    end behavioral;
     
    However, when I test the waveform to see what it would do, the signals A8, A9, B8, B9 stay low and never accept values.

    For example: CLK0 is 1, and B8 is 1, A8 remains 0 when it should be 1. Any help?
     
    John5788, Jun 17, 2008
    #1
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  2. John5788

    jeppe

    Joined:
    Mar 10, 2008
    Messages:
    348
    Location:
    Denmark
    Try this:

    The other gives "no meaning" I quess.
     
    jeppe, Jun 17, 2008
    #2
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