vhdl code generators ( crossposted in comp.hardware.fpga)

Discussion in 'VHDL' started by abe, Nov 19, 2008.

  1. abe

    abe Guest

    does anybody have a clear opinion about code generators ( c-> vhdl ,
    matlab-> vhdl, etc..) that are around? Are they really irreplaceable
    in complex applications (i.e DSP) as the vendors say?
    abe, Nov 19, 2008
    #1
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  2. abe

    Tricky Guest

    On 19 Nov, 15:47, abe <> wrote:
    > does anybody have a clear opinion about code generators ( c-> vhdl ,
    > matlab-> vhdl, etc..) that are around? Are they really irreplaceable
    > in complex applications (i.e DSP) as the vendors say?


    We recently had a talk from the guys at mathworks about Simulink.

    From what I can tell, and from the opinion of the software and
    hardware guys, is that the Software code generation is fairly mature
    and pretty good.
    We have done a simple project with VHDL code generation, and it does
    work, but I wouldnt really call it readable, or maintainable in code
    form, but the idea is all your source is the Simulink system diagrams.

    Here is an example of the code generated for a multiplier:

    signal input_a : unsigned(7 downto 0);
    signal input_b : unsigned(7 downto 0);
    signal mult_res : usngiend(15 downto 0);
    signal mult_res_resize : unsigned(7 downto );
    signal mult_res_register : unsigned(7 downto 0);
    ...
    mult_res <= input_a * input_b;
    mult_res_resize <= mult_res(15 downto 8);

    process(clk)
    begin
    if rising_edge(clk) then
    mult_res_register <= mult_res_resize;
    end if;
    end process;

    Now when you add that in with resize functions all over the page, it
    quickly becomes unreadable. We had a simple system with about 4 fixed
    point multipliers, and about 6 adders, and I wouldnt want to try and
    re-organise it for efficiancy. If it was more complex, I wouldnt even
    want to look at the output VHDL.

    It is not meant to replace hand written code, it is meant to be a
    system level specifcation that has the tools to generate code that can
    be used to put onto an FPGA. It appears to be very useful at allowing
    the user to specify what is software and what is hardware. I got the
    feeling that for more complex systems, hand written VHDL would still
    be far more maintainable and efficient for now. But it should work.

    One point to note: you will need digital electronic knowledge to
    ensure you create the hardware versions of the top level functions
    properly.
    Tricky, Nov 19, 2008
    #2
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