Vhdl Test Bench

[michsib]

i have written a test bench for correlator which needs more of improvement and i dont know what more i can do? please do help


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use work.threshold.all;
----------------------------------------------------------------------
entity correlator_min_TB is -- entity declaration
end correlator_min_TB;

----------------------------------------------------------------------

architecture TB of correlator_min_TB is

component correlator_min -- component declaration
port (
x_in : in std_logic_vector (0 to 15);
clk : in std_logic;
enable : in std_logic;
reset_n : in std_logic;
sel : in std_logic;
compare_out : out std_logic_vector (0 to 31));

end component;

signal t_x_in : std_logic_vector(0 to 15); -- signal declaration
signal t_clk : std_logic := '0';
signal t_enable : std_logic := '0';
signal t_reset_n : std_logic := '0';
signal t_compare_out : std_logic_vector (0 to 31);
signal sel : std_logic := '0';
signal err_nb : integer := 0; -- test number
signal sum : integer;
signal errors : boolean;
signal b : std_logic_vector (0 to 31); -- tell the tesbench
-- if errors have already been detected
-- checks where this step occurs to debug
-- this shoud be in the package file in order to have any file making refenrence to
-- same value
--threshold value

constant clkperiod : time := 10 ns;
constant pre: std_logic_vector(0 to 15) :="1111111111111111" ; --preamble
begin

S_correlator: correlator_min port map (
t_x_in,
t_clk,
t_enable,
t_reset_n,
sel,
t_compare_out);


process
variable a : integer;
begin
a := 2**16;
err_nb <= 0;
errors <= false;
t_reset_n <='1';
sel <= '0';
t_clk <= '0'; wait for clkperiod/2; t_clk<='1'; wait for clkperiod/2;
t_x_in <= conv_std_logic_vector(a,16); -- t_x_in <= "1111111111111111";

t_reset_n <= '0';
t_enable <= '1';
t_clk <= '0'; wait for clkperiod/2; t_clk<='1'; wait for clkperiod/2;



-- this is a brute test
-- 1 trying to check if multiplier and comparator is running fine
-- the accumulator does not sum
-- this part will show compare_out = t_x_in from max down to
-- but as this is only 10 loops , the comparator will still output x_in value

-- insert b=a*pre and test the compare_out to b

for i in 0 to 16 loop
t_x_in <= conv_std_logic_vector(a,16);
sel <= not sel;
t_clk <= '0'; wait for clkperiod/2; t_clk<='1'; wait for clkperiod/2;
a := a /2 ;
if(t_compare_out/=t_x_in) then
assert false
report "**1*** such output was not expected compare_out=" &
integer'image(conv_integer(t_compare_out)) & " expected=" & integer'image(a) severity note;
errors <=true;
err_nb <=1;
end if;
-- checking for b/= compare_out (b= a * pre)--
b <= conv_std_logic_vector(a,16) * pre;
if(t_compare_out/=b) then
assert false
report " **2***such output was not expected compare_out=" &
integer'image(conv_integer(t_compare_out)) & " expected=" & integer'image(a) severity note;
errors <=true;
err_nb <=2;
end if;

end loop;

-- second test part
-- trying to figure out the comarator result if accu < threshold =e
-- check if it is zero


a := conv_integer(dn) ;

for i in 0 to 5 loop
t_x_in <= conv_std_logic_vector(a,16);
t_clk <= '0'; wait for clkperiod/2; t_clk<='1'; wait for clkperiod/2;
a := a /2 ;
sum <= a + sum;
if(t_compare_out/=t_x_in) then
assert false
report "**3*** such output was not expected compare_out=" &
integer'image(conv_integer(t_compare_out)) & " expected=" & integer'image(sum) severity note;
errors <=true;
err_nb <=3;
end if;

end loop ;

-- third test--

a := 2**16;
sel <= '0';

for i in 0 to 10 loop
t_x_in <= conv_std_logic_vector(a,16);
sel <= not sel;
t_clk <= '0'; wait for clkperiod/2; t_clk<='1'; wait for clkperiod/2;
a := a /2 ;
sum <= (a*dn) + sum;
if i mod 2 = 0 then
sel <= not sel;
else
sum <= 0; -- clear the expected result
end if;
if(t_compare_out/=sum) then
assert false
report "**4*** such output was not expected compare_out=" &
integer'image(conv_integer(t_compare_out)) & " expected=" & integer'image(sum) severity note;
errors <=true;
err_nb <=4;
end if;

end loop ;

-- now you can display a test result

-- during the debug phase diffrents tests can help to debug and going into details
-- once the entity is debugged you have to clean up and only display the test resume
-- checking if errors = 1 or 0 if 1 the display the err number to help


wait;
end process;

end TB;