VHDL to EDIF

Discussion in 'VHDL' started by Leow Yuan Yeow, Feb 8, 2006.

  1. Hi, may I know whether there is any program that is able to convert a vhdl
    file to a .edf file? I am unable to find such options in the Xilinx ISE
    Navigator.
    Thanks!

    YY
    Leow Yuan Yeow, Feb 8, 2006
    #1
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  2. I have tried using the Xilinx ngc2edif convertor but when I tried to
    generate a bit file from the edf file its says:

    ERROR:NgdBuild:766 - The EDIF netlist 'synthetic2.edf' was created by the
    Xilinx
    NGC2EDIF program and is not a valid input netlist. Note that this EDIF
    netlist is intended for communicating timing information to third-party
    synthesis tools. Specifically, no user modifications to the contents of
    this
    file will effect the final implementation of the design.
    ERROR:NgdBuild:276 - edif2ngd exited with errors (return code 1).
    ERROR:NgdBuild:28 - Top-level input design file "synthetic2.edf" cannot be
    found
    or created. Please make sure the source file exists and is of a
    recognized
    netlist format (e.g., ngo, ngc, edif, edn, or edf).

    "Leow Yuan Yeow" <> wrote in message
    news:43e98cb4$...
    > Hi, may I know whether there is any program that is able to convert a vhdl
    > file to a .edf file? I am unable to find such options in the Xilinx ISE
    > Navigator.
    > Thanks!
    >
    > YY
    >
    Leow Yuan Yeow, Feb 8, 2006
    #2
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