FPGA - mixing edif and VHDL in Xilinx ISE?

[dkbauter]

Hi,

I'm currently stuck at following FPGA synthesis problem:

I have a VHDL RTL design ... and I have a simple behavioural model of a ROM (incl. file i/o for loading it at startup of simulation), both synthesizable.

My actual workflow is to synthesize it using Synplify within an Unix environment and then further process the resulting file incl. the specific port map under Windows using Xilinx ISE.

However, I'd like to split the workflow by synthesizing the design without the ROM code using Synplify (maybe treated as a black box) and then re-synthesize the VHDL ROM code and the the edif result file together to get a working programming file for the FPGA.

Summarized: I want to mix an edif file and a VHDL file within a Xilinx ISE project.

(Just to mention, the ROM unit is situated deeply in the hierarchy of the system)

Is this possible in general?
If it is, what is the best way to link the ROM VHDL code with the black box (especially when the ROM/black box is situated deeply within the synthesized design)?

Thanks in advance!