Visual IP Designer interresting new EDA tool

Discussion in 'VHDL' started by vdauthor, Dec 29, 2006.

  1. vdauthor

    vdauthor Guest

    You are kindly invited to visit www.visualipd.com home of Visual IP
    Designer.

    Visual IP Designer is an EDA tool for design entry and integration
    which enable designers to intuitively build, maintain and reuse their
    designs using a full graphical approach. Visual IP Designer provides an
    advanced and fast methodology to develop HDL-based designs targeting
    ASIC and FPGA. The Visual IP format is able to describe designs at RTL
    level in a more flexible and attractive way. The automatic code
    generation feature allows obtaining a high quality VHDL code optimized
    for synthesis with a non scarified readability.

    Because visual representation is closer to human way of thinking,
    Visual IP Designer target is to provide a complete range of graphical
    means of description replacing the classical textual approach. Unlike
    mixed graphical/textual solutions Visual IP Designer allow the
    graphical representation at 100% of all the aspects of RTL design.

    Visual IP Designer! benefits:
    Speed, entring and mainaining a design graphically is faster than usign
    multiple vhdl files
    Communicating and thinking graphically is more effective than using
    text
    Dynamic checking, errors are located early during the design entry
    phase
    High quality generated VHDL code, free of compilation/elaboration
    errors, ready for synthesis
    Visual IP format may be used for documentation purpose, no need for
    redundant documentation
    Visual IP allow extended generic capabilities (generic interface,
    generic mapping, etc)
    Packaging, delivering generic Visual IP format is more attractive and
    user freindly than native VHDL files
    Reuse interfaces/sub blocks is simple and fast thanks to import/export
    capabilities
    System integration, assambling Visual IPs is easy, no need for
    additional interfaces/parameters description

    Regards

    Vd author
     
    vdauthor, Dec 29, 2006
    #1
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  2. vdauthor wrote:

    > You are kindly invited to visit www.visualipd.com home of Visual IP
    > Designer.


    Your demos cannot be played in Linux. It seems they require a newer
    flash player than available for Linux.

    In the upper right corner I see that an evaluation version is
    available. Just for windows. No thanks.

    Where can it be downloaded anyhow? The download button brings me
    to: "You are not authorized to view this resource. You need to
    login."

    --
    Paul.
    www.aimcom.nl
    email address: switch x and s
     
    Paul Uiterlinden, Jan 2, 2007
    #2
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  3. vdauthor

    fpgaengineer Guest

    Re: Visual IP Designer interresting new EDA tool

    Paul Uiterlinden wrote:
    > vdauthor wrote:
    >
    > > You are kindly invited to visit www.visualipd.com home of Visual IP
    > > Designer.

    >
    > Your demos cannot be played in Linux. It seems they require a newer
    > flash player than available for Linux.
    >

    for me it doesn`t run too - although using Win. The player says
    "loading" but stops at 8%.

    Does this designer support round trip engineering by importing existing
    HDL-Designs?
    I am looking for somwting beeing able to easily discover the hierarchy.
     
    fpgaengineer, Jan 2, 2007
    #3
  4. vdauthor

    vdauthor Guest

    Re: Visual IP Designer interresting new EDA tool

    Hi Paul

    Paul Uiterlinden a écrit :

    > Your demos cannot be played in Linux. It seems they require a newer
    > flash player than available for Linux.


    Sorry for this I will try to investigate this issue and keep you
    informed

    > In the upper right corner I see that an evaluation version is
    > available. Just for windows. No thanks.


    The Linux and Solaris versions exist but not yet for evaluation. To
    be able to evaluate the tool the only possibility currently is Windows


    > Where can it be downloaded anyhow? The download button brings me
    > to: "You are not authorized to view this resource. You need to
    > login."

    This is because before to be allowed to get your evaluation copy you
    need to register and then login


    > --
    > Paul.
    > www.aimcom.nl
    > email address: switch x and s


    Thanks a lot

    Hope This Help

    VDAuthor
     
    vdauthor, Jan 4, 2007
    #4
  5. vdauthor

    vdauthor Guest

    Re: Visual IP Designer interresting new EDA tool

    Hello

    >fpgaengineer a écrit :


    > for me it doesn`t run too - although using Win. The player says
    > "loading" but stops at 8%.


    I noticed this issue for slow Internet connection. To solve the problem
    I have added with each demo its zipped package. In this way you will be
    able to download the demo and see it off-line.

    > Does this designer support round trip engineering by importing existing
    > HDL-Designs?
    > I am looking for somwting beeing able to easily discover the hierarchy.


    It is not possible to import an existing HDL-Design in its textual
    format toward the Visual IP format. This is very difficult to achieve
    unless your design is written with a strict subset of the VHDL laguage.
    But if we limit this to the hierarchy +interface+portmapping it will be
    feasible. This feature is already in the roadmap of the tool.

    Thanks a lot

    VDAuthor
     
    vdauthor, Jan 4, 2007
    #5
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