What is the meaning of "." in VHDL

Discussion in 'VHDL' started by jasonkee111, Dec 20, 2010.

  1. jasonkee111

    jasonkee111

    Joined:
    Dec 29, 2008
    Messages:
    5
    hi. I came across the dot "." in a testbench. i have no idea what is the function. Normally we will on only see it in the library declaration. However it is used in the process.

    Is there anyone know abt it?

    Thanks
    jasonkee111, Dec 20, 2010
    #1
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  2. jasonkee111

    sridar

    Joined:
    Jun 5, 2007
    Messages:
    51
    Re:

    Can you post the code snippet? Might be the elements inside the record type is accessed..
    sridar, Dec 20, 2010
    #2
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