Mike said:
I mean in the MyHDL *source*,
not the generated code.
No, .next is only for signals. Other types of objects and
assignments are supported by the convertor, and (only) those
map to variables.
Now, neither Python nor MyHDL currently support your favorite
coding style of local interfaceless procedures. This is because
of Python's current scoping rules. Perhaps that explains some
of the confusion?
Below is a small example of how MyHDL currently supports
variables that keep state, as compared to a signal. The
generated VHDL code is added. Hopefully this will make
it clearer:
============================================================
from myhdl import *
def Example(clock, reset):
count_sig = Signal(intbv(0)[8:])
@instance
def logic():
count_var = intbv(0)[8:]
while True:
yield clock.posedge, reset.negedge
if reset == 0:
count_sig.next = 0
count_var[:] = 0
else:
assert count_sig == count_var # equal
count_sig.next = count_sig + 1
count_var += 1
assert count_sig == count_var - 1 # different!
return logic
=============================================================
The generated VHDL code:
========================================================
-- File: Example.vhd
-- Generated by MyHDL 0.6
-- Date: Mon Dec 22 11:12:11 2008
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.pck_myhdl_06.all;
entity Example is
port (
clock: in std_logic;
reset: in std_logic
);
end entity Example;
architecture MyHDL of Example is
signal count_sig: unsigned(7 downto 0);
begin
EXAMPLE_LOGIC: process (clock, reset) is
variable count_var: unsigned(7 downto 0);
begin
if (reset = '0') then
count_sig <= "00000000";
count_var := "00000000";
elsif rising_edge(clock) then
assert (count_sig = count_var)
report "*** AssertionError ***"
severity error;
count_sig <= (count_sig + 1);
count_var := (count_var + 1);
assert (count_sig = (count_var - 1))
report "*** AssertionError ***"
severity error;
end if;
end process EXAMPLE_LOGIC;
end architecture MyHDL;
=====================================================
