'X' - Forcing Unknown

Discussion in 'VHDL' started by Matt North, Nov 16, 2004.

  1. Matt North

    Matt North Guest

    Hi,

    I have an entity which has a synchronous reset. Therefore the output is 'X'
    until a f_edge(clk) occurs with rst='1'.
    What would the value of 'X' be in hardware before the clock edge '0', '1' or
    either?????

    Thanks.
     
    Matt North, Nov 16, 2004
    #1
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  2. Matt North wrote:
    > Hi,
    >
    > I have an entity which has a synchronous reset. Therefore the output is 'X'
    > until a f_edge(clk) occurs with rst='1'.
    > What would the value of 'X' be in hardware before the clock edge '0', '1' or
    > either?????


    Either a '0' or a '1'.

    Paul.
     
    Paul Uiterlinden, Nov 16, 2004
    #2
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  3. Matt North

    Neo Guest

    X is dependent on the start up condition of the transistor and can be
    0 or 1 or anything inbetween.
     
    Neo, Nov 18, 2004
    #3
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