A
Alex
The VHDL source and UCF file are at the bottom of this document.
The error that I'm getting is:
NCD was not produced. All logic was removed from design. This
is usually due to having no input or output PAD connections in the
design and
no nets or symbols marked as 'SAVE'. You can either add PADs or
'SAVE'
attributes to the design, or run 'map -u' to disable logic trimming
in the
mapper.
I've got all my ports connected (see the UCF), and my logic seems right
(it's just a sample from the Xilinx "Quick Start") ... what am I
missing? I can get something simple working (like, OUTPUT(0) <=
SWITCH1; -- as the whole body), but anything more complex generates
this error.
Any help would be greatly appreciated. Thank you!
The VHDL:
entity ffff is
Port ( CLOCK : in STD_LOGIC;
DIRECTION : in STD_LOGIC;
COUNT_OUT : out STD_LOGIC_VECTOR (3 downto 0));
end ffff;
architecture Behavioral of ffff is
signal count_int : std_logic_vector(3 downto 0) := "0000";
begin
process (CLOCK)
begin
if CLOCK='1' and CLOCK'event then
if DIRECTION='1' then
count_int <= count_int + 1;
else
count_int <= count_int - 1;
end if;
end if;
end process;
COUNT_OUT <= count_int;
end Behavioral;
The UCF:
NET "CLOCK" LOC = "C9" | IOSTANDARD = LVCMOS33;
NET "CLOCK" PERIOD = 20.0ns HIGH 40%;
NET "COUNT_OUT<0>" LOC = "F12" ;
NET "COUNT_OUT<1>" LOC = "E12" ;
NET "COUNT_OUT<2>" LOC = "E11" ;
NET "COUNT_OUT<3>" LOC = "F11" ;
NET "DIRECTION" LOC = "L13" ;
The error that I'm getting is:
NCD was not produced. All logic was removed from design. This
is usually due to having no input or output PAD connections in the
design and
no nets or symbols marked as 'SAVE'. You can either add PADs or
'SAVE'
attributes to the design, or run 'map -u' to disable logic trimming
in the
mapper.
I've got all my ports connected (see the UCF), and my logic seems right
(it's just a sample from the Xilinx "Quick Start") ... what am I
missing? I can get something simple working (like, OUTPUT(0) <=
SWITCH1; -- as the whole body), but anything more complex generates
this error.
Any help would be greatly appreciated. Thank you!
The VHDL:
entity ffff is
Port ( CLOCK : in STD_LOGIC;
DIRECTION : in STD_LOGIC;
COUNT_OUT : out STD_LOGIC_VECTOR (3 downto 0));
end ffff;
architecture Behavioral of ffff is
signal count_int : std_logic_vector(3 downto 0) := "0000";
begin
process (CLOCK)
begin
if CLOCK='1' and CLOCK'event then
if DIRECTION='1' then
count_int <= count_int + 1;
else
count_int <= count_int - 1;
end if;
end if;
end process;
COUNT_OUT <= count_int;
end Behavioral;
The UCF:
NET "CLOCK" LOC = "C9" | IOSTANDARD = LVCMOS33;
NET "CLOCK" PERIOD = 20.0ns HIGH 40%;
NET "COUNT_OUT<0>" LOC = "F12" ;
NET "COUNT_OUT<1>" LOC = "E12" ;
NET "COUNT_OUT<2>" LOC = "E11" ;
NET "COUNT_OUT<3>" LOC = "F11" ;
NET "DIRECTION" LOC = "L13" ;