xilinx simprim compilation error

Discussion in 'VHDL' started by Pinhas, Aug 14, 2007.

  1. Pinhas

    Pinhas Guest

    Hello
    I am tring to compile it /simprim_VITAL.vhd with GHDL (free VHDL
    simulator) and get errors regarding:
    .....
    simprim_VITAL.vhd:153574:57: variable "write_b_read_a" is not visible
    here

    This is a vriable declared in process with strange way:
    VITALBehavior : process

    variable Tviol_ADDRA0_CLKA_posedge : std_ulogic := '0';
    .... variable Write_B_Read_A : memory_collision_type :=
    Write_B_Read_A;
    ....

    My question why to initialize with the same value (Write_B_Read_A).
     
    Pinhas, Aug 14, 2007
    #1
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  2. Pinhas

    Georg Acher Guest

    Pinhas <> writes:
    >Hello
    >I am tring to compile it /simprim_VITAL.vhd with GHDL (free VHDL
    >simulator) and get errors regarding:
    >....
    >simprim_VITAL.vhd:153574:57: variable "write_b_read_a" is not visible
    >here
    >
    >This is a vriable declared in process with strange way:
    > VITALBehavior : process
    >
    > variable Tviol_ADDRA0_CLKA_posedge : std_ulogic := '0';
    >... variable Write_B_Read_A : memory_collision_type :=
    >Write_B_Read_A;
    >...
    >
    >My question why to initialize with the same value (Write_B_Read_A).


    http://groups.google.de/group/comp....st&q=acher ghdl&rnum=7&hl=de#0bc1aafecb71755f

    --
    Georg Acher,
    http://www.lrr.in.tum.de/~acher
    "Oh no, not again !" The bowl of petunias
     
    Georg Acher, Aug 14, 2007
    #2
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