VHDL

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comp.lang.vhdl
H
Open Source VHDL Verification Methodology
  • HT-Lab
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4
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2K
HT-Lab
H
S
VHDL code error
  • suraj lulla
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1
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1K
backhus
B
V
truncating std_logic_vector multiplication result question
  • vivo_m
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1
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3K
joris
J
V
building hierarcy error
  • vivo_m
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0
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1K
vivo_m
V
V
real to std_logic_vector conversion
  • vivo_m
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1
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7K
jeppe
J
T
Detecting bit transistion in std_logic_vector
  • Tobias Baumann
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14
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2K
Tobias Baumann
T
P
vcs simulation problem
  • priyanka24
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0
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1K
priyanka24
P
A
VCS- How to use libraries
  • Anil Dalwani
Replies
2
Views
5K
priyanka24
P
J
VHDL program
  • jyothi
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0
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1K
jyothi
J
N
Sync high freq to 100Hz?
  • nivparsons
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2
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1K
KJ
K
S
DE0-Nano g-forces
  • sindredit
Replies
0
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1K
sindredit
S
D
the "Don't care" value
  • Day_1
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1
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1K
jeppe
J
J
crc-5
  • javid
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0
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964
javid
J
A
summing of array elements in for loop
  • antsor
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0
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2K
antsor
A
T
Why cant protected type methods have a parameter thats an access type?
  • Tricky
Replies
1
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1K
JimLewis
J
M
parallel CRC and ragged words
  • Matt
Replies
9
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2K
Mark Curry
M
P
Test process behaviour
  • Peter
Replies
2
Views
1K
Peter
P
M
Sanity check on a weird bit of math and std_logic_unsigned
  • M. Norton
Replies
2
Views
1K
JimLewis
J
R
Active-HDL/Xilinx Core FIFO Gen Sim Problem
  • roleohibachi
Replies
3
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2K
MBodnar
M
J
Stimulus Counter (from Opto-Sensors)
  • james.purvis
Replies
3
Views
2K
Thomas Stanka
T
O
Spartan 6 MPMC - more ports?
  • Oliver Mattos
Replies
1
Views
1K
Christopher Head
C
P
problem in verilog coding
  • priyanka24
Replies
0
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1K
priyanka24
P
V
Open file path specification
  • valtih1978
Replies
0
Views
914
valtih1978
V
C
Call For Papers: Journal of Engineering & Technology
  • Chief Editor
Replies
0
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1K
Chief Editor
C
E
Shared Variables...
  • Element Blue
Replies
10
Views
6K
vlsi.vishal
V
F
Is this a Ghdl/gtkwave bug?
  • Francesco Bonizzi
Replies
0
Views
1K
Francesco Bonizzi
F
T
Is this a Ghdl/gtkwave bug?
  • tuttoscorre
Replies
0
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1K
tuttoscorre
T
M
EPLD programming
  • mininath
Replies
0
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1K
mininath
M
T
Why isnt buffer used more often?
  • Tricky
Replies
9
Views
2K
Paul Uiterlinden
P
R
concurrent signal assignment: order can matter?
  • ralvarexo
Replies
5
Views
2K
Michael Hermann
M
F
State machine - Vending machine - strange behaviour
  • fenster
Replies
3
Views
2K
jeppe
J
S
Version control for VHDL projects.
  • Symon
2
Replies
21
Views
5K
KJ
K
M
can any one help me
  • manal
Replies
0
Views
1K
manal
M
F
A gray counter
  • fofo
Replies
3
Views
3K
eliascm
E
G
Testbench flow control with TCL
  • glw75
Replies
1
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2K
glw75
G
M
Can a vhdl function return a range?
  • mksuth
Replies
5
Views
7K
Tricky
T
M
code synthesis problem
  • manideepa
Replies
0
Views
1K
manideepa
M
D
psl assertion for dynamically created signal length
  • David Belohrad
Replies
1
Views
2K
HT-Lab
H
D
Failure: (vsim-3807) Types do not match between component and entity for port "out1".
  • deesaid
Replies
3
Views
4K
deesaid
D
N
Getting rid of packages in VHDL code
  • Nicholas Kinar
Replies
4
Views
2K
Nicholas Kinar
N
S
Converted signed 16 Bit to unsigned?
  • Steffen Koepf
Replies
1
Views
2K
Gabor
G
V
External name elaboration order
  • valtih1978
Replies
2
Views
2K
JimLewis
J
S
incremental generic association
  • sebs
Replies
3
Views
1K
JimLewis
J
R
SystemVerilog for verification
  • Rob Gaddi
Replies
9
Views
2K
JimLewis
J
D
Convolutional Encoder VHDL
  • davidspielberg
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0
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2K
davidspielberg
D
D
How to make Clock Divider
  • dadili
Replies
8
Views
8K
jeppe
J
N
Using Xilinx VHDL code with UNISIM on Altera toolset
  • Nicholas Kinar
Replies
9
Views
5K
Nicholas Kinar
N
R
Error 10500
  • rain
Replies
0
Views
3K
rain
R
S
Xilinx floating-point core example please
  • sam.green
Replies
2
Views
3K
vgs
V
L
How do you use serial port or any other bus
  • LM
Replies
6
Views
1K
valtih1978
V

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