assert of generic, during synthesis

[whygee]

Hello,

I am trying to write some portable code where
one generic parameter, if wrong, gives a
synthesis error that is difficult to understand.

More precisely, i have a constant table that
is addressed by the generic and i want to stop
synthesis when the value in the table is 0,
or something like that, with a clear message.

I wand to use "assert" but it does not seem to
be evaluated by the synthesiser.
Some googling told me that it is not abnormal.
I use synplify, by the way, and i wonder if most
synthesizers behave the same way.

Any hint or clue ?
yg

 

[whygee]

Hi Brian !
Thank you for the express answer !

Xilinx XST can handle certain forms of assert (statically determinable
conditions) during synthesis. Others it ignores, but with a warning.

ok, so i guess that the best thing to do is
forget the asserts for synthesis, i leave some
for the simulation, and I put a comment
close to where the synth says "out of range access"...

I don't expect the code to be synthesised without
a proper simulation but you never know :-D

thanks again,

- Brian.

yg

 

[KJ]

More precisely, i have a constant table that
is addressed by the generic and i want to stop
synthesis when the value in the table is 0,
or something like that, with a clear message.

If you have a generic that shouldn't be 0, then it should be defined
as a 'postive', not 'natural' or 'integer'...either that or define the
range to be '1 to ??'

KJ

 

[Jonathan Bromley]

If you have a generic that shouldn't be 0, then it should be defined
as a 'postive', not 'natural' or 'integer'...either that or define the
range to be '1 to ??'

I don't think that's terribly helpful, for two reasons.

First, an integer subtype defines only one single
contiguous range of legal values. Real-world
parameterization problems often have much more
complicated constraints on parameter values than
a simple range constraint.

Second, it's the wrong weapon. A subtype range
violation suggests that someone is abusing the
datatype system - things like trying to specify
a vector with a negative number of bits, for
example. That's a rather different idea than
"the value is inappropriate given the set of
other parameter values", which is much more
application-specific and needs specific
diagnostic messages such as can only be had
from custom assertions.

One of the great joys of VHDL over Verilog
is its very clear-headed elaboration semantics,
allowing you to write assertions over constant
values and be assured that they will be checked
at elaboration time, before simulation begins.
By contrast, Verilog has only in the most recent
version of the standard (1800-2009) gained
elaboration-time assertions, and of course
the tool support isn't there yet. In standard
Verilog you can't check parameter values until
simulation begins at time zero, which is usually
too late - by that time, your bad parameter
values are likely to have caused other fatal
errors in the simulator.

One point worth checking: some synth tools
don't trip on assertions unless they are
FATAL severity.

Generally, I would regard it as a bug if a
VHDL synth tool does not honour assertions
over constant (elaboration-time) values
such as generics.

 

[HT-Lab]

Hello, ...
Some googling told me that it is not abnormal.
I use synplify, by the way, and i wonder if most
synthesizers behave the same way.

Hi Yg,

Precision does report the assertion but only as a warning:

GENERIC(
CNTRESET : std_logic_vector(7 downto 0):="00000000");

assert ( CNTRESET /= "00000000" )
report "Count must not be zero" severity failure;

# Warning: [45547]: Assertion Failed: failure : Count must not be zero

As Jonathan mentioned it only works for failure.

Regards,
Hans.
www.ht-lab.com

 

[Tricky]

Hello, ..
Some googling told me that it is not abnormal.
I use synplify, by the way, and i wonder if most
synthesizers behave the same way.

Hi Yg,

Precision does report the assertion but only as a warning:

GENERIC(
CNTRESET : std_logic_vector(7 downto 0):="00000000");

assert ( CNTRESET /= "00000000" )
report "Count must not be zero" severity failure;

# Warning: [45547]: Assertion Failed: failure : Count must not be zero

As Jonathan mentioned it only works for failure.

Regards,
Hans.www.ht-lab.com

Any hint or clue ?
yg

This was discussed a while back - but Quartus Handles asserts properly
(and quits if it fails or errors)

 

[KJ]

If you have a generic that shouldn't be 0, then it should be defined
as a 'postive', not 'natural' or 'integer'...either that or define the
range to be '1 to ??'

KJ

Woops, I retract the above. I misread "when the value in the table is
0" as "the address specified by the generic is 0"

KJ

 

[whygee]

Woops, I retract the above. I misread "when the value in the table is
0" as "the address specified by the generic is 0"

yes,
i'm back here and i see that many people have assumed like you.
In my case, this is not a matter of testing the generic's value,
but testing the value of the table at the address givent by the
generic.

When there is an illegal value, the table returns 0,
and it should normally give an index into a vector
that is 1..N. The synth catches that last error,
but it's too late, we lost an opportunity to explain
what went wrong.

A comment in the doc "solved" this.

thank you everybody,

KJ

yg