Records & Synthesis

[Jeremy Ralph]

Any consensus on VHDL records for synthesizable RTL? If one wishes to
write portable RTL that works for most synthesizers can records be
used? Can records be safely used for ports? Or, should they only be
use internally within a component? Or, should they be avoided for RTL
code?

As I recall certain synthesis tools used to choke on arrays of vectors
in ports at the top level of a component. This seems so trivial that
it's hard to believe... certainly it scared me from experimenting
with records in RTL. Hopefully the synthesis tools of today properly
support arrays and records in ports.

So comp.lang.vhdl what are your thoughts / experiences with regard to
records in RTL?

Thanks,
Jeremy Ralph

 

[Hans]

Should be no problem, I have used records in my projects and
Precision/Spectrum/XST/QNS could all handle it. I would only suggest to
avoid using records at the top level since most (if not all) netlist writers
translate them to individual vectors.

Hans.
www.ht-lab.com

 

[Peter]

Hi,

I always use records to connect entities to each other, and have not
discovered any problems.

However, records does not seem to work on the top entity, as Hans said.

/Peter

 

[lundril]

Just as another input:

I use records with Quartus II internal synthesis and there also is no
problem.
(I only avoid this for the toplevel, since I don't know if Quartus
likes that
and I can't imagine how to do pin-assignments on a toplevel port which
is a "record".)

so long
lundril