Breaking parallel multiplier into two pieces in VHDL?

Discussion in 'VHDL' started by pap74, Jul 7, 2009.

  1. pap74

    pap74

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    Hello,

    I have a 18x10 parallel signed multiplier in my design which obviously is a very large block. It is implemented as a slow booth multiplier by Cadence RTL Compiler. I would like to reduce the size of the multiplier by breaking it into two parallel multipliers (using the same block twice) and using two clock cycles to complete the multiplication. I am not sure what the formula is that I can apply to calculate the result especially considering that the operands are signed. Could someone tell me how I may be able to do this?

    I cannot use a serial multiplier because I do not have the clock cycles.

    Thanks.
     
    Last edited: Jul 7, 2009
    pap74, Jul 7, 2009
    #1
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