Henning Bahr said:
Hi there!
I hope this isn't too trivial:
I'm having a digital system with a finite state machine and a few
other modules which send a control signal to the FSM. Do you think it
is possible to use only clock and only posedge Flip Flops in such a
design? I can't manage it without the inverted clock so that the
control signals change at half the clock signal. But is there a way to
avoid this without violating setup and hold times?
Cheers,
Henning
Henning,
I am assuming that the finite state machine and the "few other modules" are
all in the FPGA. It is very possible to do what you ask about, and it is
done day in and day out. As Peter Alfke said earlier, FPGAs are designed to
have the clock to out time be longer than the hold time, assuming the signal
propagated from Q to D input instantaneously. The only thing you have to
worry about is the sum of clock to Q time, routing time, setup time and
clock skew to be less than the clock period. That is what constraints are
for -- to tell the place and route tool to meet that timing and to quantify
it for you.
Now let's assume that you do use the opposite edge, i.e., falling edge, of
the clock. Also assume that you are not using a PLL or DLL. If the clock
is not guaranteed to be perfectly symmetrical, then you must do additional
analysis to determine what the high and low times are. You now need to
factor this timing in, using additional constraints, to determine just how
much time the tool should allow for the signal to make it to the opposite
edge, i.e., the rising edge of the flip flop. This complicates timing and
constraints, which detracts from the real task - to get a design working
efficiently in a minimal amount of time. There are reasons to use opposite
edges, but what you described above is not one of them.
What you have described above is a synchronous design with one clock domain.
Once you master a one clock design, you will be ready to move on to multiple
clock designs where circuitry can be grouped into clock domains. Then you
will have to learn how circuitry in one clock domain can talk reliably to
circuitry in another clock domain. There are special rules to achieve this
with great reliability, and it all comes under the heading of synchronous
design. From my experience, only a small percentage of companies have taken
the time and resources to document lessons learned (dating back to the
1970s) and generate design guides that cover this particular subject. These
companies covet their design guides and expect their engineers to use it
because they know it gives them a competitive edge. There are books,
though, that cover this topic. From my experience, the companies that have
not taken the time to document and generate design guides are also not
reading these books, because I see a fair amount of asynchronous design
usage, too.
Good luck to you.
Simon Ramirez, Consultant
Synchronous Design, Inc.
Oviedo, FL USA