How to implement an irragular table?

Discussion in 'VHDL' started by fl, Feb 14, 2014.

  1. fl

    fl Guest

    Hi,

    I want to implement a table, which has nonlinear input. For example, its input has 7 segmentations:

    Segmentation........... Mapping ratio
    1-511.................. 1 : 1
    512-1023............... 1 : 2
    1024-2047.............. 1 : 4
    2048-4095.............. 1 : 8
    4096-8191.............. 1 : 16
    8192-16383............. 1 : 32
    16384-32767............ 1 : 64

    Thus, the first row has 511 entries while all others have 256 entries. There are values (26 bits in wordlength) corresponding to these entries.

    I am new to VHDL. It looks like a lookup table, but the nonlinear entries make me feel difficult. Could you help me on this problem?


    Thanks,
     
    fl, Feb 14, 2014
    #1
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  2. fl

    fl Guest

    Thanks Allan. Your post really gives me some fresh view on my question. I may start in your idea later.

    After I sort through my question, I think that I care about resource cost for a Xilinx Spartan 6 now. The input has 15 bits for 0...32767 while there are total 2048 distinct value corresponding to these entries. A straight forward look up table works, which looks like a 15-bit input, 26-bit output table.

    My question now is whether there is a structure less than the above design,because there are only 2048 (11-bit, not 15-bit) output distinct values.

    Thanks,
     
    fl, Feb 16, 2014
    #2
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  3. fl

    fl Guest

    I have found a solution for my problem. It is about using stages to get the value out.
    Your method is really stimulating to me. Just one thing I need you more information.

    "For more accuracy I could have coded this table as the deviation from a
    straight line then added the input to the output, but I did not need to
    do that."

    Could you give me a little more detail on above? Thanks again.
     
    fl, Feb 16, 2014
    #3
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