weijun said:
I need to implement a module that has variable number of ports and the
width of the port is also variable (but same for all ports). Can
someone suggest a way to do that?
Thanks a lot!
If you really need a port, there are (at least) two possibilities:
- use a configuration package where you define an array of arrays
of the proper size. The sizes are best declared as constants
in that package, so they can be accessed by code across entities
(by including the package).
- use a one-dimensional port, e.g. std_logic_vector(M*N-1 downto 0)
for the port. Within the modules you can of course again use
two-dimensional arrays and just assign accordingly. In this case,
M and N can be generics.
I would strongly suggest the second solution, since complex data
structures on ports lead to problems in synthesis/netlists.
The first solution may be OK if the module is only ever used
internally and you never need to work with a (often verilog)
netlist of that module.
Robert