entity cmp is -- if A<B than Y=1 else Y=0
generic(n : natural);
port(A, B: in std_logic_vector(n - 1 downto 0);
Y : out std_logic);
end cmp;
architecture RTL of cmp is
signal sY, set : std_logic_vector(n downto 0);
signal test : std_logic_vector(n - 1 downto 0);
begin
sY(n) <= '0';
set(n) <= '1';
compare: for i in A'range generate
test(i) <= (A(i) xor B(i)) and set(i + 1);
sY(i) <= B(i) when test(i) = '1' else sY(i + 1);
set(i) <= '0' when test(i) = '1' else set(i + 1);
end generate compare;
Y <= sY(0);
end RTL;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity cmp is -- if A<B than Y=1 else Y=0
generic(n : natural);
port(A, B: in std_logic_vector(n - 1 downto 0);
Y : out std_logic);
end cmp;
architecture structural of cmp is
signal sY, set, test : std_logic_vector(n - 2 downto 0);
begin
sY(n - 2) <= (not A(n - 1)) and B(n - 1);
set(n - 2) <= A(n - 1) xnor B(n - 1);
compare: for i in n - 2 downto 1 generate
test(i) <= (A(i) xor B(i)) and set(i);
sY(i - 1) <= ((not test(i)) and sY(i)) or (test(i) and B(i));
set(i - 1) <= (not test(i)) and set(i);
end generate compare;
test(0) <= (A(0) xor B(0)) and set(0);
Y <= ((not test(0)) and sY(0)) or (test(0) and B(0));
end structural;
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