In the process of learning VHDL, I'm trying to go through the motions
of writing a simple instruction fetch stage for a processor. My
question for this group is: what is the "right" way of handling a
variable and unknown time to fetch from memory? (assuming an
handshaked interface to memory, i.e. I send a read request and wait
for a done signal to return) I'm having difficulty figuring out what
should be happening on which clock edge, mostly in the case where the
read time exceeds one clock cycle.
To enlarge a little on the correct but terse responses you've already
had: If you can live with the obvious performance consequences of
your CPU doing nothing whilst it's waiting for the fetch, you should
simply write the fetch controller state machine so that it remains
in its "twiddle thumbs until instruction available" state until
the memory ready signal comes true. Very vaguely, something like
this:
process (clock)
...
begin
if rising_edge(clock) then
...
case fetch_controller_state is
when need_new_instruction =>
read_request <= '1';
fetch_controller_state <= await_instruction;
when await_instruction =>
if memory_ready = '1' then
instr_buffer <= memory_data_bus;
fetch_controller_state <= start_decode;
--- else state remains at "await_instruction"
end if;
...
A related anecdote: A few years ago I did a toy CPU (mainly
to act as fodder for some of our course practicals) that used
the APB bus as its interface to memory. The original APB bus
has a fixed read cycle of exactly 2 clocks, so the instruction
fetch state machine was pretty simple and predictable. Later
I upgraded the state machine to support the newer APB3 bus,
which has a "ready" signal and can introduce wait states.
It took only about five or six lines of code to add
stall-until-ready logic in the way I've suggested. As
you might imagine, the CPU's performance is crap - but
that wasn't the point; and I suspect that for you, too, the
resulting performance is much less important than your
learning experience.
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
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