Modifying RTL code - How to convert a VHDL Function to a Component -2 questions

Discussion in 'VHDL' started by zeev, Apr 5, 2008.

  1. zeev

    zeev Guest

    Hello all,
    I need to do a massive surgery on an existing RTL code.
    The objective is to generate a "hard" hierarchical layer around a VHDL
    Function, by "hard" I mean that it'll be kept after synthesis - this
    will help me in tools in the Flow downstream synthesis.

    I thought about converting the function to a component first and then
    connecting it to the processes in which the original function was
    called in. This looks like "easier said than done..."

    As an alternative I would like to be able to isolate a small fraction
    of this specific, called, function, e.g. a multiplication , and have
    solid hierarchical boundary of this operation only.

    I assume a Synthesis that is non aggressive, i.e: does not ungroup in
    any way and does not do any boundary optimization.

    Any idea on how to do this will be truly appreciated.
    thx
    \ZeevY
     
    zeev, Apr 5, 2008
    #1
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  2. Maybe you mean a vhdl design entity.
    A function just returns a value and has no ports.
    That sounds like an design entity
    or an instance of a design entity.

    -- Mike Treseler
     
    Mike Treseler, Apr 5, 2008
    #2
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  3. zeev

    KJ Guest

    Help to do what? What really is the problem, and why would massive surgery
    help? If there are problems with the existing code, they will be found in
    simulation and/or static timing analysis not massive surgery without an
    understanding of why one is doing the surgery. If however you're looking to
    get data on resource usage than this might be useful since you do tend to
    get reports on logic resource usage on a 'per entity' basis.
    No it should be fairly trivial. The input parameters to the functions are
    inputs to an entity, the single output of the function is an output of the
    entity. Procedures can be converted in the same fashion.
    So convert that small fraction into an entity/architecture and connect it
    up.
    You assume incorrectly.
    I'd suggest not doing this since I doubt it will help you get to the root of
    the real problem that you're trying to solve...whatever that problem might
    actually be.

    Kevin Jennings
     
    KJ, Apr 5, 2008
    #3
  4. zeev

    radarman Guest

    1) Think carefully before tearing a design apart. Yes, it can
    sometimes help when you need to understand what is going on. However,
    I have learned from personal experience that you often create more
    problems than you solve. I used to believe that when you took over a
    design that the first thing you did was rewrite it. The trouble is,
    you now have essentially a new design with all new bugs.

    2) It should be trivial to write a VHDL component that wrappers a
    function. Just implement the function it the same way you normally
    would, but create an entity/architecture pair that isolates on the I/O
    to the function. In place of the function call, instantiate the
    wrapper, and wire up the I/O.

    I don't see why this is preferable to simply using the function "in-
    place", though. You have merely added another layer of complexity
    without really gaining much. The only time I have considered doing
    something like this was when I wanted to implement a free CRC
    calculator that came in the form of a VHDL function. I created a "bus
    wrapper" that allowed a SoC microcontroller access the function across
    a bus. The wrapper also held address decoding logic and registers, so
    it was a bit more than just a wrapper, but it more or less did what
    you are describing.
     
    radarman, Apr 9, 2008
    #4
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