multiD-vhdl: Multi Dimensional Arrays (allowing generics on each dimension) for VHDL (including port

Discussion in 'VHDL' started by albert.neu@gmail.com, Mar 20, 2006.

  1. Guest

    -- multiD-vhdl: Multidimensional Array (allowing generics) for VHDL
    -- ================================================================
    -- Version 1.0 (20 March 2006)



    -- *** Package Purpose:
    -- Multidimensional Arrays with complete control of every dimension;
    -- allowing every dimension to be specified with generics
    -- (especially useful for multi-dimensional parametizable ports)

    -- *** How is it implemented?
    -- As a 1-dimensional array, that is treated as a multi-dimensional
    -- array


    -- *** Why?
    -- VHDL (VHSIC Hardware Description Language) lacks the possiblity
    -- to define multidimensional arrays for ports,
    -- ###where each dimension can be kept generic###.

    -- It was not possible (with normal VHDL) to have multiple instances of
    -- an entity,
    -- ###where each instance can have different generics for each
    -- dimension###.

    -- This can be solved with this VHDL package (with functions), that
    -- allows a 1D array to be treated as a multidimensional array.


    -- *** Is it synthesizable?
    -- Yes: has been tested on Synplify 8.5 (tested entity: generic MUX)




    Get it here:
    http://stud4.tuwien.ac.at/~e0425408/vhdl/multiD-vhdl.zip

    License:
    LGPL


    Comments, Suggestions welcome




    =============================================
    Albert Neumüller
    21 March 2006
    =============================================








    -------------------------------------------------------------------------------
    -- QUICK Usage Examples:
    -- Requires fixed-width font (courier, etc.)
    --
    -- 1. Initializtion
    --
    -- Example: 3D - array
    -- --we want: %%% (0 to 6, 4 downto 2, 1 to 8) %%% -------->
    --
    -- constant dim_info : DD_dimensions := (0, 6, 4, 2, 1, 8);
    -- -- |--| |--| |--|
    -- -- dim0 dim1 dim2
    --
    -- signal arr3D : std_logic_vector(DD_zero to
    DD_calc_size(dim_info)-1);
    --
    --
    -- 2. Accessing sub-parts of the multiD (multi-dimensional) array:
    --
    -- Example:
    -- signal result : std_logic_vector(1 to 8);
     
    , Mar 20, 2006
    #1
    1. Advertisements

  2. Guest

    -- *** Why?
    -- VHDL (VHSIC Hardware Description Language) lacks the possiblity
    -- to define multidimensional arrays for ports,
    -- ###where each dimension can be kept generic### & where it is
    synthesizable.

    -- It was not possible (with normal VHDL) to have multiple instances of
    -- an entity,
    -- ###where each instance can have different generics for each
    -- dimension### & syntheziable.


    =============================================
    Albert Neumüller
    21 March 2006
    =============================================
     
    , Mar 20, 2006
    #2
    1. Advertisements

  3. Jim Lewis Guest

    Albert,
    Fortunately arrays of unconstrained arrays will
    be a supported feature of the Accellera VHDL-2006 revision.
    Make sure your vendors know that you want it supported.

    Cheers,
    Jim

    --
    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    Jim Lewis
    Director of Training mailto:
    SynthWorks Design Inc. http://www.SynthWorks.com
    1-503-590-4787

    Expert VHDL Training for Hardware Design and Verification
    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     
    Jim Lewis, Mar 21, 2006
    #3
    1. Advertisements

Ask a Question

Want to reply to this thread or ask your own question?

You'll need to choose a username for the site, which only take a couple of moments (here). After that, you can post your question and our members will help you out.