Whenever i synthesize i top level block in xilinx, i get this msg, "No clock signals found in design", so i dont get information about the clock speed or clock delay; this is wierd since i have a central clk signal that drives a lot of Flip flops
how do i correct this in synthesis? how do i make xilinx realize i have a clk sig that needs to be treated appropriately? i have no IBUFs, or CLKBufs in design
how do i correct this in synthesis? how do i make xilinx realize i have a clk sig that needs to be treated appropriately? i have no IBUFs, or CLKBufs in design