Mike Treseler worte:
The basis for one-hot encoding is that it might save some gates.
However when you add the fail-safe requirement to a one-hot
machine, this savings (if there really is any) goes out the window.
Another twist that synthesis may optimize out the "WHEN others" logic
in any case.
Consider binary encoding.
Thank you very much Mike. I have considered your suggestion but now I
have much similar problem to ask in in Binary Encoding..
Following is the excerpt from the synopsys
documentation...................
" Designers using VHDL often create an enumerated type for their FSM,
as shown in
the following example:
type state_type is (IDLE, S1, S2, S3,S4);
signal state, next_state : state_type;
begin
process (state, NEXT)
begin
next_state <= state;
case state is
when IDLE =>
if (NEXT) then
next_state <= S1;
end if;
when S1 =>
if (NEXT) then
next_state <= S2;
end if;
when S2 =>
if (NEXT) then
next_state <= S3;
end if;
when S3 =>
if (NEXT) then
next_state <= S4;
end if;
when S4 =>
if (NEXT) then
next_state <= IDLE;
end if;
end case;
end process;
In this example, the behavior for each of the enumerated states is
described.
However, when this code is synthesized to hardware, there will be three
remaining states in which the FSM can potentially get stuck. Using
"when
others" is not sufficient by itself to prevent problems in this
situation,
because no other enumerated states exist for this type. Consequently
dummy
states must be created to make the FSM fail-safe.
Dummy States Example
type state_type is (IDLE, S1, S2, S3, S4, S5_dummy, S6_dummy,
S7_dummy);
signal state, next_state : state_type;
begin
process (state, NEXT)
begin
next_state <= state;
case state is
when IDLE =>
if (NEXT) then
next_state <= S1;
end if;
when S1 =>
if (NEXT) then
next_state <= S2;
end if;
when S2 =>
if (NEXT) then
next_state <= S3;
end if;
when S3 =>
if (NEXT) then
next_state <= S4;
end if;
when S4 =>
if (NEXT) then
next_state <= IDLE;
end if;
when others =>
next_state <= "IDLE";
end case;
end process;
Design Compiler will report that these dummy states are unreachable
because
there are no transitions into them, but the transition logic from the
dummy
states back to the useful states will still be synthesized.
Fortunately, Design
Compiler doesn't automatically remove the unreachable dummy states.
However,
when an FSM optimization command such as fsm_enable_state_minimization
is used,
these unreachable states are optimized away. Therefore, to build a
fail-safe
FSM, do not use the FSM optimization capability."
Now I would like to ask that if a design has 17 legal states then do
I have to follow the same guidelines and create additional 15 dummy
states to accomplish fail-safe requirments. Or do we have any other
better technique for this.
Thanks..
-- Mohammed A khader.
