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Hello everyone!
I am new to VHDL. I ran into a problem of "unwanted latches". ("Latches may be generated from incomplete case or if statements."). I searched on the internet about this warning but it seems I could not find an answer that specially applies to my case.
Here are some details:
The code is a finite statement machine. When I synthesize the VHDL code, it gave me some warnings about generating latches for a few signals. I did use CASE statement.
But I think I already assigned value to every signal/variable in each case. I checked my code multiple times but still have no clue why it always gave me such a warning message.
The problemetic signals/variables in my code are "sel1_val0", "sel1_val1", "sel2_val", "sec_counter", "plane_counter".
Could some help me by taking a look into my code? I have my code in the attachment. It is too long to paste it within this thread. Thanks a lot in advance.
I am new to VHDL. I ran into a problem of "unwanted latches". ("Latches may be generated from incomplete case or if statements."). I searched on the internet about this warning but it seems I could not find an answer that specially applies to my case.
Here are some details:
The code is a finite statement machine. When I synthesize the VHDL code, it gave me some warnings about generating latches for a few signals. I did use CASE statement.
But I think I already assigned value to every signal/variable in each case. I checked my code multiple times but still have no clue why it always gave me such a warning message.
The problemetic signals/variables in my code are "sel1_val0", "sel1_val1", "sel2_val", "sec_counter", "plane_counter".
Could some help me by taking a look into my code? I have my code in the attachment. It is too long to paste it within this thread. Thanks a lot in advance.
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