real to signed

[FPGA]

How to convert real to signed. The range of real will be from -1 to 1,
-5 to 5, -10 to 10 and so on. I would like to convert this range to a
signed vector of bit width bw(generic). The data has to be scaled but
I have no idea on how to do it. I have searched on the internet and
did not find any valuable information.

 

[Symon]

How to convert real to signed. The range of real will be from -1 to 1,
-5 to 5, -10 to 10 and so on. I would like to convert this range to a
signed vector of bit width bw(generic). The data has to be scaled but
I have no idea on how to do it. I have searched on the internet and
did not find any valuable information.

Google this:-

convert real signed vhdl

Click on the first link with the left button of your mouse.

HTH., Syms.

 

[Mike Treseler]

How to convert real to signed. The range of real will be from -1 to 1,
-5 to 5, -10 to 10 and so on. I would like to convert this range to a
signed vector of bit width bw(generic). The data has to be scaled but
I have no idea on how to do it. I have searched on the internet and
did not find any valuable information.

Start with modulo arithmetic.
http://deadsmall.com/3AE

 

[Tricky]

How to convert real to signed. The range of real will be from -1 to 1,
-5 to 5, -10 to 10 and so on. I would like to convert this range to a
signed vector of bit width bw(generic). The data has to be scaled but
I have no idea on how to do it. I have searched on the internet and
did not find any valuable information.

You will need to know magnitude width and fraction width as you will
be generating a fixed point decimal.
Magnitude width (MW) can be done by taking log2(limit) and adding 1
(to account for the sign bit).
Fraction width (FW) is then bw-MW.

Then you scale the result by 2**FW and convert it to an integer (which
then gives you your signed number).
Remember Integer(my_real) always rounds to nearest. If you dont want
to round to nearest, you have to write a function that rounds to zero,
otherwise removing the LSBs will always round down. (towards 0 for
+ve, away from 0 for -ve).

 

[Paul Uiterlinden]

How to convert real to signed. The range of real will be from -1 to 1,
-5 to 5, -10 to 10 and so on.

I don't understand this.

I would like to convert this range to a
signed vector of bit width bw(generic). The data has to be scaled but
I have no idea on how to do it.

What do you mean by scaling?

I have searched on the internet and did not find any valuable information.

If it is only about converting from real to signed, then first convert the
real to integer, and then to signed with the to_signed function from
ieee.numeric_std.

Something like this:

LIBRARY ieee;
USE ieee.numeric_std.ALL;
...
FUNCTION real2signed
(
r: real;
return_width: positive
) RETURN signed IS
BEGIN
RETURN to_signed(integer(r), return_width);
END FUNCTION real2signed;

 

[Tricky]

You will need to know magnitude width and fraction width as you will
be generating a fixed point decimal.
Magnitude width (MW) can be done by taking log2(limit) and adding 1
(to account for the sign bit).
Fraction width (FW) is then bw-MW.

Then you scale the result by 2**FW and convert it to an integer (which
then gives you your signed number).
Remember Integer(my_real) always rounds to nearest. If you dont want
to round to nearest, you have to write a function that rounds to zero,
otherwise removing the LSBs will always round down. (towards 0 for
+ve, away from 0 for -ve).

PS. None of this is synthesisable, as it bases all working on reals,
which you cannot synthesise in any way. Reals are only allowed to
create constants (which then have to be of a synthesizable type).

If you are trying now to synthesize your sine wave generator, you are
going about it the wrong way.

 

[FPGA]

PS. None of this is synthesisable, as it bases all working on reals,
which you cannot synthesise in any way. Reals are only allowed to
create constants (which then have to be of a synthesizable type).

If you are trying now to synthesize your sine wave generator, you are
going about it the wrong way.- Hide quoted text -

- Show quoted text -

I dont want to synthesize this.

 

[FPGA]

I don't understand this.


What do you mean by scaling?


If it is only about converting from real to signed, then first convert the
real to integer, and then to signed with the to_signed function from
ieee.numeric_std.

real can be of type 0.0134 .. if I convert this to integer it is going
to give a 0.

 

[FPGA]

You will need to know magnitude width and fraction width as you will
be generating a fixed point decimal.
Magnitude width (MW) can be done by taking log2(limit) and adding 1
(to account for the sign bit).

MW and FW of output real changes with change in amplitude. What is
'limit'?

 

[Thomas Stanka]

How to convert real to signed. The range of real will be from -1 to 1,
-5 to 5, -10 to 10 and so on. I would like to convert this range to a
signed vector of bit width bw(generic). The data has to be scaled but
I have no idea on how to do it. I have searched on the internet and
did not find any valuable information.

Start with understanding what a real is:
http://en.wikipedia.org/wiki/IEEE_754-1985
Than it is easy to write your conversion function.

bye Thomas

 

[Tricky]

MW and FW of output real changes with change in amplitude. What is
'limit'?

You are ignoring what the MW and FW lengths of the real are, because
it uses neither. For a real, which is floating point, its not
magnitude and fraction widths, its mantissa and exponent. You are
specified what YOU want the real to fit in to. You are making a FIXED
POINT decimal value, so MW and FW never change. for example:

from 3 to -3

you need MW = 3 (1 sign bit an 1 other bit)
FW = how ever many you want. each bit represets 2^-n (with n=0 to the
left of the imaginary point)

so 0.75 is represended by: 000.1100000 = 2^-1 (0.5) + 2^-2 (0.25)
1.75 = 001.11000000 = 2^0 (1) + 2^-1 (0.5) + 2^-2 (0.25)
-1.75 = 110.01111111 (invert all bits and add one to number above)
etc
etc
All values are 2s compliment, and can then be used in any standard
adder, multiplier etc on firmware. Just make sure you use the correct
bits of the result:

a 2.6 number x 6.2 number = 8.8 result

a a . a a a a a a
b b b b b b . b b
= r r r r r r r r . r r r r r r r r

 

[FPGA]

You are ignoring what the MW and FW lengths of the real are, because
it uses neither. For a real, which is floating point, its not
magnitude and fraction widths, its mantissa and exponent. You are
specified what YOU want the real to fit in to. You are making a FIXED
POINT decimal value, so MW and FW never change. for example:

from 3 to -3

you need MW = 3  (1 sign bit an 1 other bit)
FW = how ever many you want. each bit represets 2^-n (with n=0 to the
left of the imaginary point)

so 0.75 is represended by:  000.1100000 = 2^-1 (0.5) + 2^-2 (0.25)
1.75 = 001.11000000  = 2^0 (1) + 2^-1 (0.5) + 2^-2 (0.25)
-1.75 = 110.01111111 (invert all bits and add one to number above)
etc
etc
All values are 2s compliment, and can then be used in any standard
adder, multiplier etc on firmware. Just make sure you use the correct
bits of the result:

a 2.6 number x 6.2 number = 8.8 result

              a a . a a a a a a
      b b b b b b . b b
= r r r r r r r r . r r r r r r r r- Hide quoted text -

- Show quoted text -

Thanks a bunch. Your explaination really helped.