RTL to VHDL

Discussion in 'Introductions' started by ivan gagula, Jun 22, 2016.

  1. ivan gagula

    ivan gagula

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    convert this RTL into VHDL

    input:clk,mr,x,dat[6]
    output:rdy,err,resa[3].resb[3]
    registers;rega[3]. regb[3]
    sequence:
    0. regb<=000
    1. rega <=dat [5..3]; =>(x=0)/(1)
    2.=> (dat [2..0] = 000)/(5)
    3. => (dat[5..3}> dat[2..0]/(6)
    4. rdy =1; resa =rega; resb= regb; =>(4)
    5. err =1; >=(5)
    6.regb <=regb +1; rega<=rega - dat[2..0]; => (4)

    control reset 0
     
    ivan gagula, Jun 22, 2016
    #1
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