UART Implementation

Discussion in 'VHDL' started by Anand P Paralkar, Jun 26, 2003.

  1. Hi,

    I need to implement a simple UART. By simple, I mean the UART only needs
    a transmitter which would take parallel data and shift it out serially at
    a fixed baud rate. The receiver receives serial input data at the same,
    fixed baud rate, which must be output in parallel, one byte at a time.
    In short, the UART should look something like:

    --->| |
    Parallel Data In | |-----> Tx to RS232 line driver
    --->| |
    | |
    <---| |
    Parallel Data Out | |<----- Rx from RS232 line driver
    <---| |
    | |
    | |

    The UART should perform:

    1. Start bit detection/generation.
    2. Stop bit detection/generation.
    3. Data bits sampling/transmitting.

    The UART does NOT need to have:

    1. Programmable baud rate.
    2. Programmable character length (6, 7 or 8 bits per character).
    3. Programmable stop bit length (1, 1.5 or 2 bits per character).
    4. Parity checking.
    5. RTS/CTS based or any other type of flow control.
    6. Buffering (using Rx and Tx FIFOs).
    7. Interrupt generation.

    Could you please suggest a design for the receiver section. (I have seen a
    few articles on the Internet, but most of them are "datasheets" of UARTs.
    None of them discuss the internal design.)

    I would be particularly interested in knowing how to determine the
    required clock frequency for a given baud rate in the receiver section.

    Why do people choose 3X or 16X clocks (times baud rate) in typical UART

    Thank you for your time.

    Anand P Paralkar, Jun 26, 2003
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  2. Anand P Paralkar

    Mario Trams Guest

    Anand P Paralkar wrote:

    Did you ever heard about this magic tool called "google"
    Searching for vhdl+uart returns tons of links.
    This is because you somehow have to "hit" the middle of the bit frames
    and syncronize the receiver with the incoming stream. That is, you wait
    for the start bit (sampled by the oversampling clock), then you wait
    half the time and sample the stop bit (i.e. you sample it at the 8th
    oversampling clock assuming a 16x clock). Then you wait another 16
    cycles and sample the first data bit etc.

    Assuming absolutely precise (constant) aligned sender and receiver
    clocks, you would not need this oversampling at all.
    If you know the worst case clock difference between the sender and
    the receiver and the bit length of a transmitted word, then you can
    calculate how much oversampling is required in order the guarantee
    a flawless operation. Of course, when the clocks are totally out of
    sync the oversampling won't help.

    Mario Trams, Jun 27, 2003
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  3. Check out our web site, we provide a free IP core of
    a simple UART.

    Rudolf Usselmann, Jul 7, 2003
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