viterbi implementation on actel fpga

Discussion in 'VHDL' started by pradeep, Dec 4, 2006.

  1. pradeep

    pradeep Guest

    hai,
    i need to impliment viterbi decoder 1/2 rate,k=7,hard decision.i have
    clearly understood the algorithm but in design can anybody help me?
     
    pradeep, Dec 4, 2006
    #1
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  2. Maybe google can
    http://groups-beta.google.com/groups/search?q=viterbi+decoder+vhdl

    Has this problem replaced the traffic light controller?

    -- Mike Treseler
     
    Mike Treseler, Dec 4, 2006
    #2
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  3. pradeep

    pradeep Guest

    pradeep, Dec 5, 2006
    #3
  4. Hi,
    If you implement something, _you_ write the code, if Mike gives you
    ready code fullfiling your spec, _he_ implemented the decoder. Maybe
    you are looking for soft ips, which could be adopted to fit your
    specification. Then why not starting with looking at opencores.org.
    Anyway, I expect Mike (and a lot other here) to be able to provide you
    the code after receiving the right amount of money. But it might be
    cheaper to buy a ready developed soft ip.

    bye Thomas
     
    Thomas Stanka, Dec 6, 2006
    #4
  5. pradeep

    pradeep Guest

    thanks, actually i want the exact block diagrm from which i can meet
    the timing requirement so.......
     
    pradeep, Dec 6, 2006
    #5
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