A very high level code in VHDL, is it Synthesizable?

Discussion in 'VHDL' started by ramtinraji, Jan 18, 2008.

  1. ramtinraji

    ramtinraji

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    Dear friends,

    A friend of minie has wirtten a high level code on Data Mining with VHDL and has used very high level constructs such as Linked lists.we want to know if this kind of code is SYNTHESIZABLE and if we can implement it on a Xilinx Spartan3 FPGA, using ISE tools.

    I appriciate it if somebody answers my question.

    Best Regards,

    Ramtin Raji
     
    ramtinraji, Jan 18, 2008
    #1
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