About multiple targets

Discussion in 'VHDL' started by smu, Nov 23, 2004.

  1. smu

    smu Guest

    Hello,

    Until now, I used especially the ACTEL FPGAs.
    Today, I start to use FPGAs of other manufacturers.
    It seems that it is possible to define several architectures for an
    entity but I did not find the appropriate syntax.
    Which is correct syntax to declare several architectures of an entity?
    And how selection between these different architectures can be done?

    I need this syntax because I want to optimize my design for each target.

    Thank you in advance

    smu
     
    smu, Nov 23, 2004
    #1
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  2. Mike Treseler, Nov 24, 2004
    #2
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  3. smu

    Neo Guest

    smu <> wrote in message news:<cnvmom$2k9$>...
    > Hello,
    >
    > Until now, I used especially the ACTEL FPGAs.
    > Today, I start to use FPGAs of other manufacturers.
    > It seems that it is possible to define several architectures for an
    > entity but I did not find the appropriate syntax.
    > Which is correct syntax to declare several architectures of an entity?
    > And how selection between these different architectures can be done?
    >
    > I need this syntax because I want to optimize my design for each target.
    >
    > Thank you in advance
    >
    > smu


    The syntax is :
    configuration <config_name> of <entity_name> is
    for <reqd_architecture_name>
    end for;
    end configuration <config_name>;

    previous to this you should have those architectures defined in the
    entity.
    by default if you have multiple architectures in an entity I think if
    you dont configure, then the last architecture compiled will be taken
    for simulation.

    -Neo
     
    Neo, Nov 24, 2004
    #3
  4. smu

    smu Guest

    Neo wrote:
    > smu <> wrote in message news:<cnvmom$2k9$>...
    >
    >>Hello,
    >>
    >>Until now, I used especially the ACTEL FPGAs.
    >>Today, I start to use FPGAs of other manufacturers.
    >>It seems that it is possible to define several architectures for an
    >>entity but I did not find the appropriate syntax.
    >>Which is correct syntax to declare several architectures of an entity?
    >>And how selection between these different architectures can be done?
    >>
    >>I need this syntax because I want to optimize my design for each target.
    >>
    >>Thank you in advance
    >>
    >>smu

    >
    >
    > The syntax is :
    > configuration <config_name> of <entity_name> is
    > for <reqd_architecture_name>
    > end for;
    > end configuration <config_name>;
    >
    > previous to this you should have those architectures defined in the
    > entity.
    > by default if you have multiple architectures in an entity I think if
    > you dont configure, then the last architecture compiled will be taken
    > for simulation.
    >
    > -Neo


    By supposing that we have a FOO entity and three associated
    architectures (FOO_ACTEL, FOO_ALTERA and FOO_VHDL), how can we write the
    code so that we can choose one of three possibilities?

    smu

    P.S. I had never used HDL to describe my FPGAs but only schematics.
     
    smu, Nov 24, 2004
    #4
  5. smu wrote:


    > It seems that it is possible to define several architectures for an
    > entity but I did not find the appropriate syntax.
    > Which is correct syntax to declare several architectures of an entity?
    > And how selection between these different architectures can be done?
    >
    > I need this syntax because I want to optimize my design for each target.


    Beside the possibility to select an architecture with the configuration
    as Mike an Neo have stated there is another option to achieve
    target-specific designs:
    You could use generic parameters. With them you could drive
    generate-statements as well normal if-then descisions.

    The advantage of generics yould be, that you only have to provide one
    architecture. This is especially useful, if there are only slight
    optimizations for special designs included. Bugfixing during development
    is much easier as you don't have to modify many architecture files, if
    something has to be changed.
    The disadvantage is the bigger source code which makes it harder to
    understand.

    If you have very different VHDL source for each target - take
    configurations, if there are only slight differences - take generic
    parameters.

    Ralf
     
    Ralf Hildebrandt, Nov 24, 2004
    #5
  6. smu

    jtw Guest

    -snip-
    > By supposing that we have a FOO entity and three associated architectures
    > (FOO_ACTEL, FOO_ALTERA and FOO_VHDL), how can we write the code so that we
    > can choose one of three possibilities?
    >
    > smu
    >
    > P.S. I had never used HDL to describe my FPGAs but only schematics.


    Generics in your configuration. This works wonders for simulation.

    Since the architectures would be in different files, you would select the
    appropriate one in your synthesis project file.

    JTW
     
    jtw, Nov 24, 2004
    #6
  7. smu

    Neo Guest

    smu <> wrote in message news:<co2807$pck$>...
    > Neo wrote:
    > > smu <> wrote in message news:<cnvmom$2k9$>...
    > >
    > >>Hello,
    > >>
    > >>Until now, I used especially the ACTEL FPGAs.
    > >>Today, I start to use FPGAs of other manufacturers.
    > >>It seems that it is possible to define several architectures for an
    > >>entity but I did not find the appropriate syntax.
    > >>Which is correct syntax to declare several architectures of an entity?
    > >>And how selection between these different architectures can be done?
    > >>
    > >>I need this syntax because I want to optimize my design for each target.
    > >>
    > >>Thank you in advance
    > >>
    > >>smu

    > >
    > >
    > > The syntax is :
    > > configuration <config_name> of <entity_name> is
    > > for <reqd_architecture_name>
    > > end for;
    > > end configuration <config_name>;
    > >
    > > previous to this you should have those architectures defined in the
    > > entity.
    > > by default if you have multiple architectures in an entity I think if
    > > you dont configure, then the last architecture compiled will be taken
    > > for simulation.
    > >
    > > -Neo

    >
    > By supposing that we have a FOO entity and three associated
    > architectures (FOO_ACTEL, FOO_ALTERA and FOO_VHDL), how can we write the
    > code so that we can choose one of three possibilities?
    >
    > smu
    >
    > P.S. I had never used HDL to describe my FPGAs but only schematics.



    Now suppose you have all the 3 architectures in a entity FOO then for
    choosing a particular architecture say FOO_ALTERA in the same module
    you have to write in the end:
    configuration one_of_three of FOO is
    for FOO_ALTERA
    end for;
    end configuration one_of_three;

    The same format applies with some slight changes when you choose the
    architectures in a top level module while instantiating the
    components.
     
    Neo, Nov 25, 2004
    #7
  8. smu

    rickman Guest

    smu wrote:
    >
    > Hello,
    >
    > Until now, I used especially the ACTEL FPGAs.
    > Today, I start to use FPGAs of other manufacturers.
    > It seems that it is possible to define several architectures for an
    > entity but I did not find the appropriate syntax.
    > Which is correct syntax to declare several architectures of an entity?
    > And how selection between these different architectures can be done?
    >
    > I need this syntax because I want to optimize my design for each target.


    I can't answer your question, but you might not need completely separate
    architectures for each entity. When I need to specify target specific
    hardware descriptions, I use GENERATE statements. They work a bit like
    #define in C, but can also do loops and conditionals.

    I find that I don't need to completely change my code between targets,
    just small parts like block rams and such.

    --

    Rick "rickman" Collins


    Ignore the reply address. To email me use the above address with the XY
    removed.

    Arius - A Signal Processing Solutions Company
    Specializing in DSP and FPGA design URL http://www.arius.com
    4 King Ave 301-682-7772 Voice
    Frederick, MD 21701-3110 301-682-7666 FAX
     
    rickman, Nov 28, 2004
    #8
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