array of signed with unconstrained bit width (suggestions?)

Discussion in 'VHDL' started by Victor Hannak, Nov 25, 2003.

  1. I am creating a component that accepts as input a 2-D array of signed
    signals (the numeric_std version of signed) that represent a coefficient
    matrix. However, I would like the bit-width of the signed coefficients to
    be variable as determined by a generic passed in to the component.

    Ideally, I would like to define a type in a package like thus:

    type signed_matrix_type is array (0 to 7, 0 to 7) of signed;

    And then the component would look like this:

    entity matrix_transform is
    generic (
    coeff_width : natural := 8);
    port (
    matrix_in : in signed_matrix_type(coeff_width-1 downto 0);
    matrix_out : out signed_matrix_type(coeff_width-1 downto 0));
    end entity matrix_transform;


    Obviously, this is incorrect for a variety of reasons. Nevertheless, I
    would love to entertain suggestions on how to best implement this component.
    Note that the base coefficient type must be signed because I want to
    carefully control bit widths throughout the design. Therefore, I do not
    want to use integer types/subtypes for the coefficients.

    Thanks,

    Vic.
     
    Victor Hannak, Nov 25, 2003
    #1
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  2. Victor Hannak wrote:
    > I am creating a component that accepts as input a 2-D array of signed
    > signals (the numeric_std version of signed) that represent a coefficient
    > matrix. However, I would like the bit-width of the signed coefficients to
    > be variable as determined by a generic passed in to the component.



    You might have to package the width
    and and vary it with a script or preprocessor.

    -- Mike Treseler

    library ieee; ----------------------------------------------------------------
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;

    package matrix_pkg is
    constant coeff_width : natural := 8;
    type signed_matrix_type is
    array (0 to 7, 0 to 7) of signed(coeff_width -1 downto 0);
    end package matrix_pkg;

    library ieee; ----------------------------------------------------------------
    use ieee.std_logic_1164.all;
    use work.matrix_pkg.all;

    entity matrix_transform is
    port (
    matrix_in : in signed_matrix_type;
    matrix_out : out signed_matrix_type);
    end entity matrix_transform;
     
    Mike Treseler, Nov 25, 2003
    #2
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