Asynchronous sequential always block with 2 clock signals

Discussion in 'VHDL' started by Prashanth Rao, Sep 19, 2007.

  1. Prashanth Rao

    Prashanth Rao

    Joined:
    Sep 19, 2007
    Messages:
    1
    Can anyone please give me the Verilog code which should have an asynchronous sequential always block with 2 clock signals.

    --Prashanth
     
    Prashanth Rao, Sep 19, 2007
    #1
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