Asynchronous stuff in a cyclone III device

Discussion in 'VHDL' started by Steffen Koepf, Jan 19, 2010.

  1. Hello,

    i have a cyclone III device with a synchronous design in it.
    Now i need a external memory interface to a ATMega, where
    the ATMega is the master. The ATMega uses the ALE/-Wr/-Rd
    style interface also used in the MCS51 devices.

    The problem is, that the lower address data are only valid
    for at least 5 ns after a falling edge of ALE. So i cant
    synchronise the ALE signal in my internal 100 MHz clock domain.

    Is it possible, to use a User-IO Pin for the ALE signal like
    this:

    ale : process (ExtBusALE)
    begin
    if (falling_edge(ExtBusALE) ) then
    BusAddrInt(15 downto 8) <= ExtBusAddress(15 downto 8);
    BusAddrInt(7 downto 0) <= ExtBusAD;
    end if;
    end process;

    to store the address data at a falling ALE edge?
    If not, is it possible to use a dedicated clock input for
    ALE, so that the signal is distributed to the clock inputs
    of the BusAddrInt storing registers?


    Thanks in advance,

    Steffen
    Steffen Koepf, Jan 19, 2010
    #1
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  2. Steffen Koepf wrote:
    i have a cyclone III device with a synchronous design in it.
    > Now i need a external memory interface to a ATMega, where
    > the ATMega is the master. The ATMega uses the ALE/-Wr/-Rd
    > style interface also used in the MCS51 devices.


    That is unfortunate.

    > The problem is, that the lower address data are only valid
    > for at least 5 ns after a falling edge of ALE. So i cant
    > synchronise the ALE signal in my internal 100 MHz clock domain.
    > Is it possible, to use a User-IO Pin for the ALE signal like
    > this:
    > ale : process (ExtBusALE)
    > begin
    > if (falling_edge(ExtBusALE) ) then
    > BusAddrInt(15 downto 8) <= ExtBusAddress(15 downto 8);
    > BusAddrInt(7 downto 0) <= ExtBusAD;
    > end if;
    > end process;


    .... and maybe resync to the fast clock.

    That sounds reasonable, but be sure to
    declare ALE as a clock to static timing
    along with the hold delay constraint.
    Synthesis will do it's best to meet it.

    > is it possible to use a dedicated clock input for
    > ALE, so that the signal is distributed to the clock inputs
    > of the BusAddrInt storing registers?


    It couldn't hurt.
    Once ALE is a known clock, it will likely get a
    global clock node if one is available.

    -- Mike Treseler
    Mike Treseler, Jan 20, 2010
    #2
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